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48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7467d 10h /.
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7476d 07h /.
46 Fixed slave address MSB='1' bug rherveille 7551d 07h /.
45 Added slave address configurability rherveille 7551d 07h /.
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 7636d 10h /.
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7636d 10h /.
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 7646d 08h /.
41 This commit was manufactured by cvs2svn to create tag 'asyst_2'. 7646d 08h /.
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7646d 08h /.
39 Forgot an 'end if' :-/ rherveille 7666d 03h /.
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7669d 11h /.
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7706d 03h /.
36 Fixed cmd_ack generation item (no bug). rherveille 7821d 04h /.
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7854d 18h /.
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7858d 16h /.
33 Fixed a bug in the Command Register declaration. rherveille 7881d 02h /.
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7891d 01h /.
31 Core is now a Multimaster I2C controller. rherveille 7895d 02h /.
30 Small code simplifications rherveille 7895d 02h /.
29 Core is now a Multimaster I2C controller rherveille 7895d 03h /.
28 *** empty log message *** rherveille 7920d 20h /.
27 Cleaned up code rherveille 7920d 20h /.
26 *** empty log message *** rherveille 7924d 04h /.
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7952d 00h /.
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7952d 00h /.
23 *** empty log message *** rherveille 8079d 06h /.
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8089d 11h /.
21 no message rherveille 8175d 11h /.
20 Added Appendix A rherveille 8175d 11h /.
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8179d 08h /.

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