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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 5114d 14h /.
75 Fixed sSDA generation rherveille 5120d 11h /.
74 Added SCL/SDA line filter rherveille 5259d 08h /.
73 Fixed double wishbone write in a single access rherveille 5259d 08h /.
72 Fixed AL generation
Added median filter on SDA and SCL inputs		 rherveille 5259d 08h /.
71 Fixed double wishbone write in a single access rherveille 5259d 08h /.
70 Added old uploaded documents to new repository. root 5567d 11h /.
69 Added old uploaded documents to new repository. root 5568d 02h /.
68 New directory structure. root 5568d 02h /.
67 Fixed slave_wait clocked event syntax rherveille 5601d 04h /.
66 Fixed type iscl_oen instead of scl_oen rherveille 5616d 03h /.
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5616d 13h /.
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5616d 14h /.
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5616d 14h /.
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5617d 04h /.
61 Removed synopsys link; it's not used rherveille 6271d 15h /.
60 Added missing semicolons ';' on endif rherveille 6448d 12h /.
59 fixed short scl high pulse after clock stretch rherveille 6453d 13h /.
58 fixed (n)ack generation rherveille 6485d 15h /.
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6485d 15h /.
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.		 rherveille 7038d 13h /.
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7039d 15h /.
54 Fixed scl, sda delay. rherveille 7039d 15h /.
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7335d 12h /.
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7335d 13h /.
51 Fixed simulation issue when writing to CR register rherveille 7389d 14h /.
50 *** empty log message *** rherveille 7404d 08h /.
49 Added testbench rherveille 7404d 09h /.
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7405d 16h /.
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7414d 12h /.

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