| Rev |
Log message |
Author |
Age |
Path |
| 45 |
Updated the flash, and the flash test bench, for Quad I/O read commands. |
dgisselq |
2837d 07h |
/. |
| 44 |
Fixed the flash so that it now runs in 1) high speed (41MHz), and 2) that it
doesn't struggle to do read bursts. This should greatly speed up access time. |
dgisselq |
2837d 07h |
/. |
| 43 |
Cleaned up the CPU memory documentation. |
dgisselq |
2837d 07h |
/. |
| 42 |
Fixed up the CPU so that it passes a multiply test bench, in addition to the
CPU test. |
dgisselq |
2837d 07h |
/. |
| 41 |
Added the CPU test program to the Arty distribution. This works. |
dgisselq |
2837d 07h |
/. |
| 40 |
Fixed a problem with the declaration of variables to be volatile. |
dgisselq |
2837d 08h |
/. |
| 39 |
Fixes the OLED test so that it runs using the DMA. |
dgisselq |
2837d 08h |
/. |
| 38 |
ZipLoad can now load programs to non-reset locations. |
dgisselq |
2837d 08h |
/. |
| 37 |
Updated documentation and copyright. |
dgisselq |
2837d 08h |
/. |
| 36 |
Lots of changes, see the git changelog for details. |
dgisselq |
2843d 17h |
/. |
| 35 |
Added comments and copyright notice. |
dgisselq |
2847d 04h |
/. |
| 34 |
These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work. |
dgisselq |
2847d 06h |
/. |
| 33 |
Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver. |
dgisselq |
2852d 12h |
/. |
| 32 |
Brought the CPU to its first working version, to include demo. |
dgisselq |
2853d 15h |
/. |
| 31 |
Initial network is now working. Adding CPU control files to repository. |
dgisselq |
2854d 08h |
/. |
| 30 |
Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz. |
dgisselq |
2854d 08h |
/. |
| 29 |
Here's the memory pin list, necessary for running Xilinx's Memory Interface
Generator. |
dgisselq |
2882d 04h |
/. |
| 28 |
Including the updates and corrections from the wbuart32 project. |
dgisselq |
2882d 05h |
/. |
| 27 |
Bus changes ... |
dgisselq |
2882d 05h |
/. |
| 26 |
Adjusted the timing comments. |
dgisselq |
2882d 05h |
/. |
| 25 |
The memory now works. However, the core speed has been lowered to 81.25MHz
to do this. The top level file is no longer fasttop.v, but toplevel.v. |
dgisselq |
2890d 13h |
/. |
| 24 |
Here are the updates from the first (failed) attempt to try to integrate
the DDR3 SDRAM controller onto this board. |
dgisselq |
2909d 08h |
/. |
| 23 |
Includes settings necessary for the Arty to load from flash builds, and to
reconfigure itself later. |
dgisselq |
2919d 08h |
/. |
| 22 |
A useful script for programming the device, given that the current device
program includes a valid comms interface. |
dgisselq |
2919d 08h |
/. |
| 21 |
Removed the OLED controller one additional clock from the bus. This was
necessary to maintain the 200MHz clock speed, especially given the growing
fanout of the device bus. |
dgisselq |
2919d 08h |
/. |
| 20 |
Lots of bug fixes: After turning on XIP, and running in XIP mode, leaving XIP
mode turns it back off again, necessitating a new write to the VCon register.
Further, XIP mode starts in extended SPI mode, and only transfers in QSPI
mode for data. Finally, two new commands have been created: enabling the
SPI memory reset, and actually resetting the SPI memory. In general, these
are all better--as the EQSPI flash controller now works with these changes,
whereby it didn't really work without them before. |
dgisselq |
2919d 08h |
/. |
| 19 |
Creates an LED mask portion of writing to the LED's register. Only those
bits specified in the mask (bits [7:4]) will be adjusted in the LED
register on a write. Hence to set all on, set the LED register to 0x0ff,
all off, 0x0f0, or to set LED 0 to on while leaving the others unchanged,
set it to 0x011. |
dgisselq |
2919d 08h |
/. |
| 18 |
The device can now program and configure itself, allowing bootstrap possibilities.
` |
dgisselq |
2919d 08h |
/. |
| 17 |
Fixed the misaddressed I/O peripherals in the fastio peripheral group. In
particular, UART and GPS were misaddressed. This has now been fixed, so these
peripherals (should) match the spec. Further, the default speed of the two
UARTs has been adjusted to 115200/8N1 for the aux UART, and 9600/8N1 for the
GPS UART. The Aux UART transmitter also passes testing, so at least that one
works. |
dgisselq |
2921d 07h |
/. |
| 16 |
This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects. |
dgisselq |
2921d 08h |
/. |
