OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [.] - Rev 208

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
208 Initial checkin with working port to or1k chris 8308d 15h /.
207 Several major changes to allow gdb to work with an Or1k implementation
that does not need a writeable PC. This version will use the breakpoint
vector and install a new vector into the EPC register, and then single
step out of the breakpoint exception. The breakpoint exception vector
must include only 2 commands: l.rfe and l.nop. Anything else and this
gdb version will fail w/ or1ksim.		 chris 8308d 18h /.
206 Several modifications to support gdb in a new exception style mode.
This new version works with gdb, and does not require the simulator
to implement a writeable PC.		 chris 8308d 18h /.
205 Adding debug capabilities. Half done. lampret 8312d 22h /.
204 Added function prototypes to stop gcc from complaining erez 8315d 13h /.
203 Updated from xess branch. lampret 8317d 03h /.
202 changed configure.in and acconfig.h to check for long long
reran autoheader & autoconf		 erez 8322d 10h /.
201 readfunc() and writefunc() now use unsigned long values instead of unsigned char. erez 8322d 10h /.
200 Initial import simons 8325d 18h /.
199 Initial import simons 8325d 19h /.
198 Moved from testbench.old simons 8328d 06h /.
197 This is not used any more. simons 8328d 06h /.
196 Configuration SPRs added. simons 8328d 06h /.
195 New test added. simons 8328d 06h /.
194 Fixed a bug for little endian architectures. Could cause a hang of
gdb under some circumstances.		 chris 8328d 14h /.
193 Declared RISCOP.RESET to be volatile so that -O2 optimization would
not optimize away the correct behavior by trying to be too clever.		 chris 8328d 15h /.
192 Removed GlobalMode reference causing problems for --disable-debugmod
option.		 chris 8329d 00h /.
191 Added UART jitter var to sim config chris 8329d 20h /.
190 Added jitter initialization chris 8329d 20h /.
189 fixed mode handling for tick facility chris 8329d 20h /.
188 fixed PIC interrupt controller chris 8329d 20h /.
187 minor change to clear pending exception chris 8329d 20h /.
186 major change to UART structure chris 8329d 20h /.
185 major change to UART code chris 8329d 20h /.
184 modified decode for trace debugging chris 8329d 20h /.
183 changed special case for PICSR chris 8329d 20h /.
182 updated exception handling procedures chris 8329d 20h /.
181 Added trace/stall commands chris 8329d 20h /.
180 Updated debug. lampret 8330d 02h /.
179 Sim run script lampret 8349d 19h /.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.