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[/] [8051/] [tags/] [rel_1/] [rtl] - Rev 145

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Rev Log message Author Age Path
145 fix bug in case of sequence of inc dptr instrucitons. simont 7737d 13h /8051/tags/rel_1/rtl
144 chsnge comp.des to des1 simont 7737d 14h /8051/tags/rel_1/rtl
143 add wire sub_result, conect it to des_acc and des1. simont 7737d 14h /8051/tags/rel_1/rtl
142 optimize state machine. simont 7738d 15h /8051/tags/rel_1/rtl
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7738d 16h /8051/tags/rel_1/rtl
140 cahnge assigment to pc_wait (remove istb_o) simont 7738d 16h /8051/tags/rel_1/rtl
139 add aditional alu destination to solve critical path. simont 7739d 10h /8051/tags/rel_1/rtl
138 Change buffering to save one clock per instruction. simont 7739d 10h /8051/tags/rel_1/rtl
137 change to fit xrom. simont 7739d 16h /8051/tags/rel_1/rtl
136 registering outputs. simont 7739d 16h /8051/tags/rel_1/rtl
135 prepared start of receiving if ren is not active. simont 7745d 15h /8051/tags/rel_1/rtl
134 fix bug in case execution of two data dependent instructions. simont 7745d 15h /8051/tags/rel_1/rtl
133 fix bug in substraction. simont 7745d 18h /8051/tags/rel_1/rtl
132 change branch instruction execution (reduse needed clock periods). simont 7749d 09h /8051/tags/rel_1/rtl
128 chance idat_ir to 24 bit wide simont 7758d 16h /8051/tags/rel_1/rtl
127 fix bug (cyc_o and stb_o) simont 7758d 16h /8051/tags/rel_1/rtl
126 define OC8051_XILINX_RAMB added simont 7758d 16h /8051/tags/rel_1/rtl
123 fiz bug iv pcs operation. simont 7760d 12h /8051/tags/rel_1/rtl
122 deifne OC8051_ROM added simont 7763d 16h /8051/tags/rel_1/rtl
121 Change pc add value from 23'h to 16'h simont 7763d 16h /8051/tags/rel_1/rtl
120 defines for pherypherals added simont 7764d 13h /8051/tags/rel_1/rtl
119 remove signal sbuf_txd [12:11] simont 7764d 17h /8051/tags/rel_1/rtl
118 change wr_sft to 2 bit wire. simont 7765d 10h /8051/tags/rel_1/rtl
117 Register oc8051_sfr dato output, add signal wait_data. simont 7765d 10h /8051/tags/rel_1/rtl
116 change sfr's interface. simont 7767d 11h /8051/tags/rel_1/rtl
115 change uart to meet timing. simont 7767d 13h /8051/tags/rel_1/rtl
114 remove t2mod register simont 7770d 16h /8051/tags/rel_1/rtl
113 signal prsc_ow added. simont 7770d 16h /8051/tags/rel_1/rtl
112 change timers to meet timing specifications (add divider with 12) simont 7770d 16h /8051/tags/rel_1/rtl
110 change adr_i and adr_o length. simont 7771d 07h /8051/tags/rel_1/rtl

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