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[/] [8051/] [tags/] [rel_1] - Rev 106

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Rev Log message Author Age Path
106 generic_dpram used simont 7805d 11h /8051/tags/rel_1
105 generic_dpram used simont 7805d 11h /8051/tags/rel_1
104 use generic_dpram simont 7805d 11h /8051/tags/rel_1
103 rename signals simont 7805d 12h /8051/tags/rel_1
102 raname signals. simont 7805d 12h /8051/tags/rel_1
101 initial inport simont 7805d 16h /8051/tags/rel_1
100 use \ simont 7805d 16h /8051/tags/rel_1
99 change directory structure simont 7805d 16h /8051/tags/rel_1
98 move to rtl/verilog simont 7805d 16h /8051/tags/rel_1
97 initial inport simont 7805d 16h /8051/tags/rel_1
96 initial import simont 7805d 16h /8051/tags/rel_1
95 updating... simont 7805d 16h /8051/tags/rel_1
94 fix bug. simont 7805d 16h /8051/tags/rel_1
93 OC8051_XILINX_RAM added simont 7805d 16h /8051/tags/rel_1
92 initial inport simont 7805d 16h /8051/tags/rel_1
91 *** empty log message *** simont 7805d 16h /8051/tags/rel_1
90 change module name. simont 7810d 10h /8051/tags/rel_1
89 Replaced oc8051_ram by generic_dpram. rherveille 7871d 13h /8051/tags/rel_1
88 fix bugs simont 7876d 13h /8051/tags/rel_1
87 add include oc8051_defines.v simont 7876d 14h /8051/tags/rel_1
86 initial input simont 7876d 14h /8051/tags/rel_1
85 prepare bugs simont 7876d 14h /8051/tags/rel_1
84 remove wb_bus_mon simont 7884d 13h /8051/tags/rel_1
83 replace some modules simont 7884d 13h /8051/tags/rel_1
82 replace some modules simont 7884d 13h /8051/tags/rel_1
81 initial import simont 7884d 13h /8051/tags/rel_1
80 removing unused modules simont 7884d 13h /8051/tags/rel_1
79 initial import simont 7884d 14h /8051/tags/rel_1
78 alu with registered outputs simont 7944d 13h /8051/tags/rel_1
77 substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel simont 7953d 10h /8051/tags/rel_1

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