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[/] [8051/] [tags/] [rel_12/] [rtl/] - Rev 174

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Rev Log message Author Age Path
174 ram modules added. simont 7694d 04h /8051/tags/rel_12/rtl
173 simualtion `ifdef added simont 7694d 04h /8051/tags/rel_12/rtl
172 BIST signals added. simont 7697d 03h /8051/tags/rel_12/rtl
171 fix bug in DA operation. simont 7705d 01h /8051/tags/rel_12/rtl
158 fix bug. simont 7709d 06h /8051/tags/rel_12/rtl
153 `ifdef added. simont 7711d 00h /8051/tags/rel_12/rtl
152 sub_result output added. simont 7711d 00h /8051/tags/rel_12/rtl
151 remove pc_r register. simont 7711d 00h /8051/tags/rel_12/rtl
150 fix some bugs. simont 7711d 00h /8051/tags/rel_12/rtl
149 pipelined acces to axternal instruction interface added. simont 7711d 00h /8051/tags/rel_12/rtl
148 include "8051_defines" added. simont 7711d 01h /8051/tags/rel_12/rtl
146 fix bug in movc intruction. simont 7733d 01h /8051/tags/rel_12/rtl
145 fix bug in case of sequence of inc dptr instrucitons. simont 7738d 05h /8051/tags/rel_12/rtl
144 chsnge comp.des to des1 simont 7738d 05h /8051/tags/rel_12/rtl
143 add wire sub_result, conect it to des_acc and des1. simont 7738d 05h /8051/tags/rel_12/rtl
142 optimize state machine. simont 7739d 06h /8051/tags/rel_12/rtl
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7739d 08h /8051/tags/rel_12/rtl
140 cahnge assigment to pc_wait (remove istb_o) simont 7739d 08h /8051/tags/rel_12/rtl
139 add aditional alu destination to solve critical path. simont 7740d 02h /8051/tags/rel_12/rtl
138 Change buffering to save one clock per instruction. simont 7740d 02h /8051/tags/rel_12/rtl
137 change to fit xrom. simont 7740d 07h /8051/tags/rel_12/rtl
136 registering outputs. simont 7740d 07h /8051/tags/rel_12/rtl
135 prepared start of receiving if ren is not active. simont 7746d 06h /8051/tags/rel_12/rtl
134 fix bug in case execution of two data dependent instructions. simont 7746d 06h /8051/tags/rel_12/rtl
133 fix bug in substraction. simont 7746d 09h /8051/tags/rel_12/rtl
132 change branch instruction execution (reduse needed clock periods). simont 7750d 00h /8051/tags/rel_12/rtl
128 chance idat_ir to 24 bit wide simont 7759d 08h /8051/tags/rel_12/rtl
127 fix bug (cyc_o and stb_o) simont 7759d 08h /8051/tags/rel_12/rtl
126 define OC8051_XILINX_RAMB added simont 7759d 08h /8051/tags/rel_12/rtl
123 fiz bug iv pcs operation. simont 7761d 03h /8051/tags/rel_12/rtl

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