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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_decoder.v] - Rev 186

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186 root 5546d 14h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
185 root 5602d 16h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7681d 08h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
179 add /* synopsys xx_case */ to case statments. simont 7681d 09h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
149 pipelined acces to axternal instruction interface added. simont 7709d 12h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
142 optimize state machine. simont 7737d 18h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7737d 20h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
139 add aditional alu destination to solve critical path. simont 7738d 14h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
132 change branch instruction execution (reduse needed clock periods). simont 7748d 12h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
118 change wr_sft to 2 bit wire. simont 7764d 13h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7764d 14h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
82 replace some modules simont 7850d 15h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
62 fix bugs in instruction interface simont 7932d 13h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
54 cahnge interface to instruction rom simont 7938d 11h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
46 prepared header simont 7955d 12h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
40 added sigals for interacting with external ram simont 7975d 16h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
23 mul & div use 4 clocks simont 7995d 10h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
20 multiplier and divider changed so they complete in 4 cycles markom 7995d 18h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
17 fix some bugs simont 7999d 16h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
10 % replaced with ^ in uart; some minor improvements markom 8000d 20h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
9 removed unused compare states markom 8002d 13h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
8 some IDS optimizations markom 8002d 13h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
5 more linter corrections; 2 tests still fail markom 8002d 17h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
4 Code repaired to satisfy the linter; testbech fails markom 8002d 18h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v
2 Initial CVS import simont 8018d 16h /8051/tags/rel_12/rtl/verilog/oc8051_decoder.v

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