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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Rev 172

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172 BIST signals added. simont 7723d 09h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
148 include "8051_defines" added. simont 7737d 07h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
144 chsnge comp.des to des1 simont 7764d 11h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7765d 14h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
139 add aditional alu destination to solve critical path. simont 7766d 08h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
134 fix bug in case execution of two data dependent instructions. simont 7772d 12h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
132 change branch instruction execution (reduse needed clock periods). simont 7776d 06h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
122 deifne OC8051_ROM added simont 7790d 13h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
120 defines for pherypherals added simont 7791d 11h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
118 change wr_sft to 2 bit wire. simont 7792d 07h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7792d 08h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7798d 04h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
102 raname signals. simont 7799d 08h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
82 replace some modules simont 7878d 09h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7947d 06h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7955d 09h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7960d 06h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 7966d 05h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
46 prepared header simont 7983d 06h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
37 added signals ack, stb and cyc simont 8010d 08h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
28 remove syn signal simont 8021d 12h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8021d 14h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
19 combinatorial loop removed simont 8024d 04h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
17 fix some bugs simont 8027d 10h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
12 des1_r in alu port list simont 8028d 08h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
9 removed unused compare states markom 8030d 07h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
8 some IDS optimizations markom 8030d 07h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 8030d 08h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
5 more linter corrections; 2 tests still fail markom 8030d 10h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
4 Code repaired to satisfy the linter; testbech fails markom 8030d 12h /8051/tags/rel_12/rtl/verilog/oc8051_top.v

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