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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Rev 181

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Rev Log message Author Age Path
181 Simulation reports added. simont 7744d 17h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
174 ram modules added. simont 7756d 02h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
172 BIST signals added. simont 7759d 01h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
148 include "8051_defines" added. simont 7772d 22h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
144 chsnge comp.des to des1 simont 7800d 03h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7801d 06h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
139 add aditional alu destination to solve critical path. simont 7802d 00h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
134 fix bug in case execution of two data dependent instructions. simont 7808d 04h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
132 change branch instruction execution (reduse needed clock periods). simont 7811d 22h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
122 deifne OC8051_ROM added simont 7826d 05h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
120 defines for pherypherals added simont 7827d 03h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
118 change wr_sft to 2 bit wire. simont 7827d 23h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7827d 23h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7833d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
102 raname signals. simont 7835d 00h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
82 replace some modules simont 7914d 01h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7982d 22h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7991d 00h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7995d 22h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 8001d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
46 prepared header simont 8018d 22h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
37 added signals ack, stb and cyc simont 8046d 00h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
28 remove syn signal simont 8057d 04h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 8057d 06h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
19 combinatorial loop removed simont 8059d 20h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
17 fix some bugs simont 8063d 02h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
12 des1_r in alu port list simont 8064d 00h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
9 removed unused compare states markom 8065d 23h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
8 some IDS optimizations markom 8065d 23h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 8066d 00h /8051/tags/rel_12/rtl/verilog/oc8051_top.v

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