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[/] [8051/] [tags/] [rel_12/] [rtl/] [verilog/] [oc8051_top.v] - Rev 186

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186 root 5546d 13h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
185 root 5602d 15h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
182 This commit was manufactured by cvs2svn to create tag 'rel_12'. 7681d 07h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
181 Simulation reports added. simont 7681d 07h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
174 ram modules added. simont 7692d 15h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
172 BIST signals added. simont 7695d 14h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
148 include "8051_defines" added. simont 7709d 12h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
144 chsnge comp.des to des1 simont 7736d 16h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7737d 19h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
139 add aditional alu destination to solve critical path. simont 7738d 13h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
134 fix bug in case execution of two data dependent instructions. simont 7744d 17h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
132 change branch instruction execution (reduse needed clock periods). simont 7748d 11h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
122 deifne OC8051_ROM added simont 7762d 18h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
120 defines for pherypherals added simont 7763d 16h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
118 change wr_sft to 2 bit wire. simont 7764d 12h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
117 Register oc8051_sfr dato output, add signal wait_data. simont 7764d 13h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
107 Include instruction cache. simont 7770d 09h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
102 raname signals. simont 7771d 13h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
82 replace some modules simont 7850d 14h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
76 add module oc8051_sfr, 256 bytes internal ram simont 7919d 11h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
72 fix bug in interface to external data ram simont 7927d 14h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
62 fix bugs in instruction interface simont 7932d 12h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
54 cahnge interface to instruction rom simont 7938d 10h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
46 prepared header simont 7955d 11h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
37 added signals ack, stb and cyc simont 7982d 13h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
28 remove syn signal simont 7993d 17h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 7993d 19h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
19 combinatorial loop removed simont 7996d 09h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
17 fix some bugs simont 7999d 15h /8051/tags/rel_12/rtl/verilog/oc8051_top.v
12 des1_r in alu port list simont 8000d 13h /8051/tags/rel_12/rtl/verilog/oc8051_top.v

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