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[/] [8051/] [tags/] [rel_12/] [rtl] - Rev 134

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Rev Log message Author Age Path
134 fix bug in case execution of two data dependent instructions. simont 7767d 04h /8051/tags/rel_12/rtl
133 fix bug in substraction. simont 7767d 07h /8051/tags/rel_12/rtl
132 change branch instruction execution (reduse needed clock periods). simont 7770d 22h /8051/tags/rel_12/rtl
128 chance idat_ir to 24 bit wide simont 7780d 05h /8051/tags/rel_12/rtl
127 fix bug (cyc_o and stb_o) simont 7780d 05h /8051/tags/rel_12/rtl
126 define OC8051_XILINX_RAMB added simont 7780d 05h /8051/tags/rel_12/rtl
123 fiz bug iv pcs operation. simont 7782d 01h /8051/tags/rel_12/rtl
122 deifne OC8051_ROM added simont 7785d 05h /8051/tags/rel_12/rtl
121 Change pc add value from 23'h to 16'h simont 7785d 05h /8051/tags/rel_12/rtl
120 defines for pherypherals added simont 7786d 03h /8051/tags/rel_12/rtl
119 remove signal sbuf_txd [12:11] simont 7786d 07h /8051/tags/rel_12/rtl
118 change wr_sft to 2 bit wire. simont 7786d 23h /8051/tags/rel_12/rtl
117 Register oc8051_sfr dato output, add signal wait_data. simont 7787d 00h /8051/tags/rel_12/rtl
116 change sfr's interface. simont 7789d 01h /8051/tags/rel_12/rtl
115 change uart to meet timing. simont 7789d 02h /8051/tags/rel_12/rtl
114 remove t2mod register simont 7792d 05h /8051/tags/rel_12/rtl
113 signal prsc_ow added. simont 7792d 05h /8051/tags/rel_12/rtl
112 change timers to meet timing specifications (add divider with 12) simont 7792d 05h /8051/tags/rel_12/rtl
110 change adr_i and adr_o length. simont 7792d 20h /8051/tags/rel_12/rtl
109 add `include "oc8051_defines.v" simont 7792d 20h /8051/tags/rel_12/rtl
108 fix some bugs, use oc8051_cache_ram. simont 7792d 20h /8051/tags/rel_12/rtl
107 Include instruction cache. simont 7792d 20h /8051/tags/rel_12/rtl
105 generic_dpram used simont 7793d 23h /8051/tags/rel_12/rtl
104 use generic_dpram simont 7793d 23h /8051/tags/rel_12/rtl
102 raname signals. simont 7794d 00h /8051/tags/rel_12/rtl
95 updating... simont 7794d 04h /8051/tags/rel_12/rtl
94 fix bug. simont 7794d 04h /8051/tags/rel_12/rtl
93 OC8051_XILINX_RAM added simont 7794d 04h /8051/tags/rel_12/rtl
92 initial inport simont 7794d 04h /8051/tags/rel_12/rtl
90 change module name. simont 7798d 22h /8051/tags/rel_12/rtl

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