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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [tags/] [rel_2/] - Rev 77

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Rev Log message Author Age Path
77 substitute modules oc8051_ram_wr_sel and oc8051ram_rd_sel with oc8051_ram_addr_sel simont 7921d 09h /8051/tags/rel_2
76 add module oc8051_sfr, 256 bytes internal ram simont 7921d 09h /8051/tags/rel_2
75 initial import simont 7921d 09h /8051/tags/rel_2
74 add module oc8051_wb_iinterface simont 7929d 10h /8051/tags/rel_2
73 initial import simont 7929d 10h /8051/tags/rel_2
72 fix bug in interface to external data ram simont 7929d 12h /8051/tags/rel_2
71 add cache simont 7933d 12h /8051/tags/rel_2
70 initial import simont 7933d 12h /8051/tags/rel_2
69 add parameters simont 7933d 13h /8051/tags/rel_2
68 add instruction cache and DELAY parameters for external ram, rom simont 7933d 13h /8051/tags/rel_2
67 add parameters for instruction cache simont 7933d 13h /8051/tags/rel_2
66 added xrom_test simont 7934d 10h /8051/tags/rel_2
65 add oc8051_icache and oc8051_cache_ram simont 7934d 10h /8051/tags/rel_2
64 signal es_int=1'b0 simont 7934d 10h /8051/tags/rel_2
63 initial import simont 7934d 10h /8051/tags/rel_2
62 fix bugs in instruction interface simont 7934d 10h /8051/tags/rel_2
61 fix bug simont 7935d 12h /8051/tags/rel_2
60 initial inport simont 7936d 13h /8051/tags/rel_2
59 add external rom simont 7940d 08h /8051/tags/rel_2
58 add external rom testing simont 7940d 08h /8051/tags/rel_2
57 add module oc8051_xrom simont 7940d 08h /8051/tags/rel_2
56 initial CVS input simont 7940d 08h /8051/tags/rel_2
55 added parameter DELAY simont 7940d 08h /8051/tags/rel_2
54 cahnge interface to instruction rom simont 7940d 08h /8051/tags/rel_2
53 initial CVS inport simont 7940d 08h /8051/tags/rel_2
52 fix bugs simont 7940d 08h /8051/tags/rel_2
51 fix bugs simont 7942d 13h /8051/tags/rel_2
50 fix bugs simont 7942d 14h /8051/tags/rel_2
49 verification added simont 7949d 13h /8051/tags/rel_2
48 added program for rom converting simont 7957d 09h /8051/tags/rel_2

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