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[/] [8051/] [tags/] [rel_2/] [bench/] [verilog] - Rev 186

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Rev Log message Author Age Path
186 root 5611d 07h /8051/tags/rel_2/bench/verilog
185 root 5667d 08h /8051/tags/rel_2/bench/verilog
180 This commit was manufactured by cvs2svn to create tag 'rel_2'. 7746d 01h /8051/tags/rel_2/bench/verilog
167 add readmem for ea. simont 7771d 12h /8051/tags/rel_2/bench/verilog
166 Change test monitor from ports to external data memory. simont 7772d 05h /8051/tags/rel_2/bench/verilog
165 remove dumpvars. simont 7772d 09h /8051/tags/rel_2/bench/verilog
157 change data output. simont 7772d 11h /8051/tags/rel_2/bench/verilog
156 add FREQ paremeter. simont 7772d 11h /8051/tags/rel_2/bench/verilog
125 update, add prescaler, rclk, tclk. simont 7822d 12h /8051/tags/rel_2/bench/verilog
124 add support for external rom from xilinx ramb4 simont 7822d 12h /8051/tags/rel_2/bench/verilog
120 defines for pherypherals added simont 7828d 09h /8051/tags/rel_2/bench/verilog
111 Remove instruction cache and wb_interface simont 7835d 03h /8051/tags/rel_2/bench/verilog
103 rename signals simont 7836d 07h /8051/tags/rel_2/bench/verilog
97 initial inport simont 7836d 10h /8051/tags/rel_2/bench/verilog
84 remove wb_bus_mon simont 7915d 07h /8051/tags/rel_2/bench/verilog
74 add module oc8051_wb_iinterface simont 7992d 05h /8051/tags/rel_2/bench/verilog
68 add instruction cache and DELAY parameters for external ram, rom simont 7996d 08h /8051/tags/rel_2/bench/verilog
59 add external rom simont 8003d 03h /8051/tags/rel_2/bench/verilog
46 prepared header simont 8020d 04h /8051/tags/rel_2/bench/verilog
37 added signals ack, stb and cyc simont 8047d 07h /8051/tags/rel_2/bench/verilog
4 Code repaired to satisfy the linter; testbech fails markom 8067d 11h /8051/tags/rel_2/bench/verilog
2 Initial CVS import simont 8083d 08h /8051/tags/rel_2/bench/verilog

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