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[/] [8051/] [tags/] [rel_2] - Rev 34

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Rev Log message Author Age Path
34 specification docunemt simont 7986d 07h /8051/tags/rel_2
33 fix some bugs simont 7986d 13h /8051/tags/rel_2
32 overflow repaired simont 7986d 13h /8051/tags/rel_2
31 fix some bugs simont 7993d 06h /8051/tags/rel_2
30 mode 1 and 3 divide clooak with 31 or 16, mode 2 with 64 or 32 simont 7996d 12h /8051/tags/rel_2
29 fix some bugs simont 7996d 13h /8051/tags/rel_2
28 remove syn signal simont 7996d 13h /8051/tags/rel_2
27 fix some bugs simont 7996d 13h /8051/tags/rel_2
26 main divider logic was optimized not optimized by compiler, so I did it by hand markom 7996d 15h /8051/tags/rel_2
25 divider and multiplier pass test markom 7997d 09h /8051/tags/rel_2
24 intensively tests all instructions markom 7997d 14h /8051/tags/rel_2
23 mul & div use 4 clocks simont 7998d 05h /8051/tags/rel_2
22 fix some bugs simont 7998d 05h /8051/tags/rel_2
21 mul bug fixed markom 7998d 10h /8051/tags/rel_2
20 multiplier and divider changed so they complete in 4 cycles markom 7998d 12h /8051/tags/rel_2
19 combinatorial loop removed simont 7999d 05h /8051/tags/rel_2
18 rst signal added simont 8002d 10h /8051/tags/rel_2
17 fix some bugs simont 8002d 10h /8051/tags/rel_2
16 inputs ram and op2 removed simont 8002d 10h /8051/tags/rel_2
15 commbinatorial loop removed simont 8002d 10h /8051/tags/rel_2
14 added signal ea_int simont 8002d 12h /8051/tags/rel_2
13 some bug fix simont 8003d 09h /8051/tags/rel_2
12 des1_r in alu port list simont 8003d 09h /8051/tags/rel_2
11 des2_r removed simont 8003d 09h /8051/tags/rel_2
10 % replaced with ^ in uart; some minor improvements markom 8003d 15h /8051/tags/rel_2
9 removed unused compare states markom 8005d 07h /8051/tags/rel_2
8 some IDS optimizations markom 8005d 08h /8051/tags/rel_2
7 immediate1 & immediate2 registers moved to oc8051_immediate_sel markom 8005d 09h /8051/tags/rel_2
6 psw combinatorial loop removed markom 8005d 11h /8051/tags/rel_2
5 more linter corrections; 2 tests still fail markom 8005d 11h /8051/tags/rel_2

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