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URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] - Rev 163

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Rev Log message Author Age Path
163 initial inport simont 7765d 02h /8051/trunk
162 initial inport. simont 7765d 02h /8051/trunk
161 fix file names. simont 7765d 02h /8051/trunk
160 initial inport. simont 7765d 02h /8051/trunk
159 initial inport. simont 7765d 03h /8051/trunk
158 fix bug. simont 7765d 03h /8051/trunk
157 change data output. simont 7765d 03h /8051/trunk
156 add FREQ paremeter. simont 7765d 03h /8051/trunk
155 add aditional tests. simont 7765d 03h /8051/trunk
154 File name fixed. simont 7765d 22h /8051/trunk
153 `ifdef added. simont 7766d 21h /8051/trunk
152 sub_result output added. simont 7766d 21h /8051/trunk
151 remove pc_r register. simont 7766d 21h /8051/trunk
150 fix some bugs. simont 7766d 21h /8051/trunk
149 pipelined acces to axternal instruction interface added. simont 7766d 21h /8051/trunk
148 include "8051_defines" added. simont 7766d 21h /8051/trunk
146 fix bug in movc intruction. simont 7788d 22h /8051/trunk
145 fix bug in case of sequence of inc dptr instrucitons. simont 7794d 01h /8051/trunk
144 chsnge comp.des to des1 simont 7794d 01h /8051/trunk
143 add wire sub_result, conect it to des_acc and des1. simont 7794d 02h /8051/trunk
142 optimize state machine. simont 7795d 03h /8051/trunk
141 remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide. simont 7795d 04h /8051/trunk
140 cahnge assigment to pc_wait (remove istb_o) simont 7795d 04h /8051/trunk
139 add aditional alu destination to solve critical path. simont 7795d 22h /8051/trunk
138 Change buffering to save one clock per instruction. simont 7795d 22h /8051/trunk
137 change to fit xrom. simont 7796d 03h /8051/trunk
136 registering outputs. simont 7796d 03h /8051/trunk
135 prepared start of receiving if ren is not active. simont 7802d 03h /8051/trunk
134 fix bug in case execution of two data dependent instructions. simont 7802d 03h /8051/trunk
133 fix bug in substraction. simont 7802d 05h /8051/trunk

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