OpenCores
URL https://opencores.org/ocsvn/aemb/aemb/trunk

Subversion Repositories aemb

[/] [aemb/] [trunk/] [rtl/] [verilog] - Rev 209

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
209 Working EAR/ESR. sybreon 5483d 22h /aemb/trunk/rtl/verilog
207 WORKING exceptions\! sybreon 5491d 17h /aemb/trunk/rtl/verilog
206 partially working exceptions. sybreon 5491d 17h /aemb/trunk/rtl/verilog
205 initial edk63 code with exception sybreon 5491d 17h /aemb/trunk/rtl/verilog
204 added initial exception handler in the pipeline. sybreon 5491d 17h /aemb/trunk/rtl/verilog
203 optimised exception signals. sybreon 5491d 17h /aemb/trunk/rtl/verilog
202 added basic exception signals. sybreon 5491d 17h /aemb/trunk/rtl/verilog
191 New directory structure. root 5621d 20h /aemb/trunk/rtl/verilog
190 Housekeeping. sybreon 5636d 06h /aemb/trunk/rtl/verilog
189 *** empty log message *** sybreon 5844d 05h /aemb/trunk/rtl/verilog
188 *** empty log message *** sybreon 5844d 05h /aemb/trunk/rtl/verilog
187 nc sybreon 5858d 17h /aemb/trunk/rtl/verilog
186 added tool specific conditional defines. sybreon 5858d 17h /aemb/trunk/rtl/verilog
172 single thread design sybreon 5898d 05h /aemb/trunk/rtl/verilog
171 *** empty log message *** sybreon 5898d 17h /aemb/trunk/rtl/verilog
170 initial sybreon 5898d 17h /aemb/trunk/rtl/verilog
169 *** empty log message *** sybreon 5898d 17h /aemb/trunk/rtl/verilog
168 *** empty log message *** sybreon 5898d 17h /aemb/trunk/rtl/verilog
167 *** empty log message *** sybreon 5898d 17h /aemb/trunk/rtl/verilog
166 final upload sybreon 5898d 17h /aemb/trunk/rtl/verilog
160 minor typo. sybreon 5924d 00h /aemb/trunk/rtl/verilog
159 Backported Adder from AEMB2_EDK62.
Fixes 64-bit math problem reported by M. Ettus.
sybreon 5924d 00h /aemb/trunk/rtl/verilog
158 Got rid of the Greater-Than comparator.
Other minor size optimisations.
sybreon 5934d 02h /aemb/trunk/rtl/verilog
157 Added interrupt capability. sybreon 5934d 06h /aemb/trunk/rtl/verilog
150 Optimisations. sybreon 5937d 06h /aemb/trunk/rtl/verilog
149 Minor performance optimisation. sybreon 5937d 13h /aemb/trunk/rtl/verilog
148 added iwb_tag_o signal tied to MSR_ICE. sybreon 5937d 18h /aemb/trunk/rtl/verilog
147 Disconnect from pipeline. sybreon 5937d 22h /aemb/trunk/rtl/verilog
140 Fixed minor typos. sybreon 5937d 22h /aemb/trunk/rtl/verilog
134 Minor performance improvements. sybreon 5938d 20h /aemb/trunk/rtl/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.