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[/] [aemb/] [trunk/] [rtl] - Rev 50

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Rev Log message Author Age Path
50 Parameterised optional components. sybreon 6121d 22h /aemb/trunk/rtl
48 Fixed spurious interrupt latching during long bus cycles (spotted by J Lee). sybreon 6126d 07h /aemb/trunk/rtl
45 Minor code cleanup. sybreon 6127d 04h /aemb/trunk/rtl
44 Added better (beta) interrupt support.
Changed MSR_IE to disabled at reset as per MB docs.		 sybreon 6127d 17h /aemb/trunk/rtl
41 New EDK 3.2 compatible design with optional barrel-shifter and multiplier.
Fixed various minor data hazard bugs.
Code compatible with -O0/1/2/3/s generated code.		 sybreon 6128d 09h /aemb/trunk/rtl
39 Made some changes to the interrupt control. In some cases, the interrupt logic waits forever and doesn't execute. Bug was discovered by M. Ettus. sybreon 6138d 17h /aemb/trunk/rtl
38 Added interrupt support. sybreon 6283d 18h /aemb/trunk/rtl
36 Removed asynchronous reset signal. sybreon 6297d 04h /aemb/trunk/rtl
35 Added async BRA/DLY signals for future clock, reset, and interrupt features. sybreon 6298d 00h /aemb/trunk/rtl
34 Corrected speed issues after rev 1.9 update. sybreon 6298d 14h /aemb/trunk/rtl
33 Fixed minor data hazard bug spotted by Matt Ettus. sybreon 6313d 21h /aemb/trunk/rtl
31 Removed byte acrobatics. sybreon 6313d 21h /aemb/trunk/rtl
28 Fixed simulation bug. sybreon 6316d 21h /aemb/trunk/rtl
27 Removed some unnecessary bubble control. sybreon 6317d 08h /aemb/trunk/rtl
26 Fixed minor synthesis bug. sybreon 6317d 08h /aemb/trunk/rtl
25 Added code documentation.
Improved size & speed of rtl/verilog/aeMB_aslu.v		 sybreon 6317d 12h /aemb/trunk/rtl
24 Made minor performance optimisations. sybreon 6317d 22h /aemb/trunk/rtl
23 Fixed minor simulation bug. sybreon 6318d 14h /aemb/trunk/rtl
22 Added support for 8-bit and 16-bit data types. sybreon 6318d 14h /aemb/trunk/rtl
19 Added initial unified memory core. sybreon 6331d 00h /aemb/trunk/rtl
18 Moved testbench into /sim/verilog.
Simulation cleanups.		 sybreon 6331d 16h /aemb/trunk/rtl
17 Cosmetic changes sybreon 6332d 20h /aemb/trunk/rtl
16 Added pipeline stalling from incomplete bus cycles.
Separated sync and async portions of code.		 sybreon 6333d 08h /aemb/trunk/rtl
14 Added initial interrupt/exception support. sybreon 6339d 23h /aemb/trunk/rtl
11 Removed unused signals sybreon 6340d 06h /aemb/trunk/rtl
10 Fixed minor bugs sybreon 6340d 07h /aemb/trunk/rtl
9 Extended testbench code sybreon 6340d 07h /aemb/trunk/rtl
8 Fixed memory read-write data hazard sybreon 6340d 07h /aemb/trunk/rtl
7 Added CMP instruction sybreon 6340d 07h /aemb/trunk/rtl
5 Fixed endian correction issues on data bus. sybreon 6340d 22h /aemb/trunk/rtl

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