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[/] [amber] - Rev 52

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Rev	Log message	Author	Age	Path
52	Fixed typo in notes on creating DDR memory interfaces using coregen	csantifort	4696d 10h	/amber
51	Revert vmlinux back to 48.	csantifort	4737d 10h	/amber
50	Revert to previous version	csantifort	4737d 10h	/amber
49	Added a note n how to change timeouts	csantifort	4737d 10h	/amber
48	Fixed a bug in linux that caused the os to not return to the running application after an interrupt. Hello-world now runs stand-alone again. Added initrd-200k-dhry, a disk image that uses the dhry program for init.	csantifort	4741d 16h	/amber
47	Changed V6 VCo from 1000Mhz to 1200 MHz	csantifort	4761d 14h	/amber
46	svn ignore vmlinux.dis and vmlinux.mem	csantifort	4769d 12h	/amber
45	Store vmlinux.mem and vmlinux.dis in compressed form	csantifort	4769d 12h	/amber
44	Updated vmlinux image based on last change	csantifort	4769d 12h	/amber
43	Added support for the flat executable file format to vmlinux, so that the hello-world program is correctly relocated when it is loaded at the end of the vmlinux test. Changed the Virtex-5 clock configuration to use a 1200MHz VCO frequency and 80MHz system clock frequency.	csantifort	4769d 12h	/amber
42	Added write buffer - fixes bug if wishbone writes takes multiple cycles to complete	csantifort	4787d 09h	/amber
41	Added instructions on how to use Coregen to create the Spartan-6 DDR3 memory interface.	csantifort	4788d 17h	/amber
40	Added wishbone bus jitter testing option. Cleaned up waveform log .do files, now seperate files for a23 and a25 cores. Added vmlinux executable elf file for running on hardware.	csantifort	4793d 09h	/amber
39	Added a second level of buffering to a25_wishbone_buf to fix a lockup bug when write acks to not return immediately, and also to improve performance slightly	csantifort	4794d 10h	/amber
38	support 128-bit wishbone now used for a25 core	csantifort	4795d 10h	/amber
37	128-bit wide boot memory module	csantifort	4796d 08h	/amber
36	Changed boot_mem for the a25 system to be 128 bits wide to match the 128-bit wide wishbone bus	csantifort	4796d 09h	/amber
35	Amber25 improvements: Use 128-bit wishbone bus, instead of 32-bit to reduce cache miss fetch times Use a fast barrel shifter for shifts between 0 and 4 to improve timing Use a 2 cycle full barrel shifter for complex shifts	csantifort	4797d 17h	/amber
34	Tweaked strcpy function to speed it up slightly	csantifort	4798d 13h	/amber
33	Fixed bug in div assembly function. Handles negative numbers correctly. Fixed bug in printf function, negative numbers now print correctly.	csantifort	4799d 10h	/amber
32	Added clock cycle counting register to test_module to support dhrystone performance measurement	csantifort	4800d 10h	/amber
31	Added dhrystone benchmark test	csantifort	4800d 10h	/amber
30	Bug fix - a write access was sometimes dropped when it was in a sequence of writes with variable wb_ack delays	csantifort	4813d 16h	/amber
29	Use lgo command for saving waveforms in modelsim	csantifort	4815d 10h	/amber
28	Moved function prototypes to .h file	csantifort	4815d 11h	/amber
27	Got working with cadence nc simulator	csantifort	4848d 17h	/amber
26	Added wish list	csantifort	4853d 18h	/amber
25	Bug fix: boot-loader.mem became larger that the allowed 8k byte boot mem size. Removed a struct in elfsplitter.c thats only used for debug - this reduced boot-loader.mem enough so that it fits again. Tidy up: Removed a debug message from hw/tools/run.sh	csantifort	4855d 15h	/amber
24	Added instructions how to build Linux kernel from source files	csantifort	4857d 15h	/amber
23	Split the source files list into a Vertex-6 only list and a Spartan-6 only list. That way users don;t need to delete files from the list manually if they only have a setup for one of the FPGA types.	csantifort	4857d 16h	/amber

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