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[/] [can/] [tags/] [rel_11/] [rtl/] [verilog/] [can_bsp.v] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5638d 06h /can/tags/rel_11/rtl/verilog/can_bsp.v
105 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7708d 00h /can/tags/rel_11/rtl/verilog/can_bsp.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7708d 00h /can/tags/rel_11/rtl/verilog/can_bsp.v
102 Little fixes (to fix warnings). mohor 7710d 15h /can/tags/rel_11/rtl/verilog/can_bsp.v
100 Synchronization changed. mohor 7714d 17h /can/tags/rel_11/rtl/verilog/can_bsp.v
95 Virtual silicon ram instances added. simons 7720d 05h /can/tags/rel_11/rtl/verilog/can_bsp.v
93 synthesis full_case parallel_case fixed. mohor 7725d 16h /can/tags/rel_11/rtl/verilog/can_bsp.v
90 paralel_case and full_case compiler directives added to case statements. mohor 7726d 14h /can/tags/rel_11/rtl/verilog/can_bsp.v
80 Form error was detected when stuff bit occured at the end of crc. mohor 7730d 12h /can/tags/rel_11/rtl/verilog/can_bsp.v
79 Bit stuffing corrected when stuffing comes at the end of the crc. tadejm 7731d 12h /can/tags/rel_11/rtl/verilog/can_bsp.v
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.		 mohor 7731d 12h /can/tags/rel_11/rtl/verilog/can_bsp.v
75 When switching to tx, sync stage is overjumped. mohor 7736d 12h /can/tags/rel_11/rtl/verilog/can_bsp.v
48 Actel APA ram supported. mohor 7838d 03h /can/tags/rel_11/rtl/verilog/can_bsp.v
45 When a dominant bit was detected at the third bit of the intermission and
node had a message to transmit, bit_stuff error could occur. Fixed.		 mohor 7848d 02h /can/tags/rel_11/rtl/verilog/can_bsp.v
44 When bit error occured while active error flag was transmitted, counter was
not incremented.		 mohor 7848d 03h /can/tags/rel_11/rtl/verilog/can_bsp.v
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7848d 11h /can/tags/rel_11/rtl/verilog/can_bsp.v
36 Most of the registers added. Registers "arbitration lost capture", "error code
capture" + few more still need to be added.		 mohor 7850d 02h /can/tags/rel_11/rtl/verilog/can_bsp.v
35 Several registers added. Not finished, yet. mohor 7853d 06h /can/tags/rel_11/rtl/verilog/can_bsp.v
32 abort_tx added. Bit destuff fixed. mohor 7855d 12h /can/tags/rel_11/rtl/verilog/can_bsp.v
31 Wishbone interface added. mohor 7857d 01h /can/tags/rel_11/rtl/verilog/can_bsp.v
30 CAN is working according to the specification. WB interface and more
registers (status, IRQ, ...) needs to be added.		 mohor 7857d 10h /can/tags/rel_11/rtl/verilog/can_bsp.v
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7858d 07h /can/tags/rel_11/rtl/verilog/can_bsp.v
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7859d 00h /can/tags/rel_11/rtl/verilog/can_bsp.v
26 Backup. mohor 7863d 09h /can/tags/rel_11/rtl/verilog/can_bsp.v
25 *** empty log message *** mohor 7863d 11h /can/tags/rel_11/rtl/verilog/can_bsp.v
24 backup. mohor 7868d 01h /can/tags/rel_11/rtl/verilog/can_bsp.v
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).		 mohor 7882d 12h /can/tags/rel_11/rtl/verilog/can_bsp.v
21 Data is stored to fifo at the end of ack stage. mohor 7883d 04h /can/tags/rel_11/rtl/verilog/can_bsp.v
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7883d 05h /can/tags/rel_11/rtl/verilog/can_bsp.v
19 RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. mohor 7883d 11h /can/tags/rel_11/rtl/verilog/can_bsp.v

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