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[/] [can/] [tags/] [rel_23/] [bench/] [verilog/] [can_testbench.v] - Rev 161

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161 New directory structure. root 5607d 21h /can/tags/rel_23/bench/verilog/can_testbench.v
148 This commit was manufactured by cvs2svn to create tag 'rel_23'. 7204d 05h /can/tags/rel_23/bench/verilog/can_testbench.v
140 I forgot to thange one signal name. igorm 7424d 23h /can/tags/rel_23/bench/verilog/can_testbench.v
139 Signal bus_off_on added. igorm 7424d 23h /can/tags/rel_23/bench/verilog/can_testbench.v
130 mbist signals updated according to newest convention markom 7578d 10h /can/tags/rel_23/bench/verilog/can_testbench.v
127 Fixing the core to be Bosch VHDL Reference compatible. mohor 7594d 20h /can/tags/rel_23/bench/verilog/can_testbench.v
119 Artisan RAMs added. mohor 7636d 06h /can/tags/rel_23/bench/verilog/can_testbench.v
83 cs_can_i is used only when WISHBONE interface is not used. mohor 7700d 01h /can/tags/rel_23/bench/verilog/can_testbench.v
68 CAN inturrupt is active low. mohor 7783d 05h /can/tags/rel_23/bench/verilog/can_testbench.v
63 ALE changes on negedge of clk. mohor 7794d 21h /can/tags/rel_23/bench/verilog/can_testbench.v
61 Bidirectional port_0_i changed to port_0_io.
input cs_can changed to cs_can_i.		 mohor 7797d 10h /can/tags/rel_23/bench/verilog/can_testbench.v
60 rd_i and wr_i are active high signals. If 8051 is connected, these two signals
need to be negated one level higher.		 mohor 7797d 12h /can/tags/rel_23/bench/verilog/can_testbench.v
59 8051 interface added (besides WISHBONE interface). Selection is made in
can_defines.v file.		 mohor 7797d 12h /can/tags/rel_23/bench/verilog/can_testbench.v
52 tx_o is now tristated signal. tx_oen and tx_o combined together. mohor 7804d 01h /can/tags/rel_23/bench/verilog/can_testbench.v
50 Top level signal names changed. mohor 7804d 01h /can/tags/rel_23/bench/verilog/can_testbench.v
48 Actel APA ram supported. mohor 7807d 17h /can/tags/rel_23/bench/verilog/can_testbench.v
39 CAN core finished. Host interface added. Registers finished.
Synchronization to the wishbone finished.		 mohor 7818d 02h /can/tags/rel_23/bench/verilog/can_testbench.v
38 Temporary backup version (still fully operable). mohor 7819d 16h /can/tags/rel_23/bench/verilog/can_testbench.v
35 Several registers added. Not finished, yet. mohor 7822d 20h /can/tags/rel_23/bench/verilog/can_testbench.v
34 Errors monitoring improved. arbitration_lost improved. mohor 7825d 02h /can/tags/rel_23/bench/verilog/can_testbench.v
31 Wishbone interface added. mohor 7826d 15h /can/tags/rel_23/bench/verilog/can_testbench.v
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7827d 22h /can/tags/rel_23/bench/verilog/can_testbench.v
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7828d 14h /can/tags/rel_23/bench/verilog/can_testbench.v
26 Backup. mohor 7832d 23h /can/tags/rel_23/bench/verilog/can_testbench.v
25 *** empty log message *** mohor 7833d 02h /can/tags/rel_23/bench/verilog/can_testbench.v
24 backup. mohor 7837d 15h /can/tags/rel_23/bench/verilog/can_testbench.v
22 Form error supported. When receiving messages, last bit of the end-of-frame
does not generate form error. Receiver goes to the idle mode one bit sooner.
(CAN specification ver 2.0, part B, page 57).		 mohor 7852d 03h /can/tags/rel_23/bench/verilog/can_testbench.v
20 CRC checking fixed (when bitstuff occurs at the end of a CRC sequence). mohor 7852d 19h /can/tags/rel_23/bench/verilog/can_testbench.v
19 RX state machine fixed to receive "remote request" frames correctly. No data bytes are written to fifo when such frames are received. mohor 7853d 02h /can/tags/rel_23/bench/verilog/can_testbench.v
18 When a frame with "remote request" is received, no data is stored to fifo, just the frame information (identifier, ...). Data length that is stored is the received data length and not the actual data length that is stored to fifo. mohor 7853d 03h /can/tags/rel_23/bench/verilog/can_testbench.v

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