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[/] [can/] [trunk/] [rtl/] [verilog/] [can_btl.v] - Rev 161

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Rev Log message Author Age Path
161 New directory structure. root 5572d 15h /can/trunk/rtl/verilog/can_btl.v
149 Fixed synchronization problem in real hardware when 0xf is used for TSEG1. igorm 7166d 16h /can/trunk/rtl/verilog/can_btl.v
141 Core improved to pass all tests with the Bosch VHDL Reference system. igorm 7334d 19h /can/trunk/rtl/verilog/can_btl.v
137 Header changed. mohor 7428d 20h /can/trunk/rtl/verilog/can_btl.v
126 Error counters fixed to be compatible with Bosch VHDL reference model.
Small synchronization changes.		 mohor 7560d 10h /can/trunk/rtl/verilog/can_btl.v
125 Synchronization changed, error counters fixed. mohor 7564d 16h /can/trunk/rtl/verilog/can_btl.v
108 Fixed according to the linter. mohor 7635d 21h /can/trunk/rtl/verilog/can_btl.v
106 Unused signal removed. mohor 7641d 19h /can/trunk/rtl/verilog/can_btl.v
104 Synchronization fixed. In some strange cases it didn't work according to
the VHDL reference model.		 tadejm 7642d 09h /can/trunk/rtl/verilog/can_btl.v
102 Little fixes (to fix warnings). mohor 7644d 23h /can/trunk/rtl/verilog/can_btl.v
100 Synchronization changed. mohor 7649d 01h /can/trunk/rtl/verilog/can_btl.v
88 Previous change removed. When resynchronization occurs we go to seg1
stage. sync stage does not cause another start of seg1 stage.		 mohor 7661d 20h /can/trunk/rtl/verilog/can_btl.v
87 When hard_sync or resync occure we need to go to seg1 segment. Going to
sync segment is in that case blocked.		 mohor 7661d 20h /can/trunk/rtl/verilog/can_btl.v
84 clk_cnt reduced from [8:0] to [6:0]. mohor 7664d 19h /can/trunk/rtl/verilog/can_btl.v
82 Removed few signals. mohor 7664d 20h /can/trunk/rtl/verilog/can_btl.v
78 tx_point generated one clk earlier. rx_i registered. Data corrected when
using extended mode.		 mohor 7665d 21h /can/trunk/rtl/verilog/can_btl.v
77 Synchronization is also needed when transmitting a message. mohor 7668d 20h /can/trunk/rtl/verilog/can_btl.v
76 Counters width changed. mohor 7668d 20h /can/trunk/rtl/verilog/can_btl.v
75 When switching to tx, sync stage is overjumped. mohor 7670d 20h /can/trunk/rtl/verilog/can_btl.v
35 Several registers added. Not finished, yet. mohor 7787d 14h /can/trunk/rtl/verilog/can_btl.v
29 Overload fixed. Hard synchronization also enabled at the last bit of
interframe.		 mohor 7792d 16h /can/trunk/rtl/verilog/can_btl.v
28 Bosch license warning added. Error counters finished. Overload frames
still need to be fixed.		 mohor 7793d 08h /can/trunk/rtl/verilog/can_btl.v
24 backup. mohor 7802d 09h /can/trunk/rtl/verilog/can_btl.v
15 Temporary version (backup). mohor 7822d 17h /can/trunk/rtl/verilog/can_btl.v
11 Acceptance filter added. mohor 7825d 08h /can/trunk/rtl/verilog/can_btl.v
10 Backup version. mohor 7836d 06h /can/trunk/rtl/verilog/can_btl.v
9 Header changed, testbench improved to send a frame (crc still missing). mohor 7837d 10h /can/trunk/rtl/verilog/can_btl.v
7 Tripple sampling supported. mohor 7838d 09h /can/trunk/rtl/verilog/can_btl.v
6 Commented lines removed. mohor 7838d 11h /can/trunk/rtl/verilog/can_btl.v
5 Synchronization working. mohor 7838d 20h /can/trunk/rtl/verilog/can_btl.v

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