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[/] [dbg_interface/] [tags/] [asyst_2/] - Rev 147

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Rev Log message Author Age Path
147 CPU_WR_CTRL and CPU_RD_CTRL defines changed. igorm 7390d 23h /dbg_interface/tags/asyst_2
146 Changes for the FormalPRO. igorm 7394d 20h /dbg_interface/tags/asyst_2
145 Support for 2 CPUs added. igorm 7395d 00h /dbg_interface/tags/asyst_2
144 Port names and defines for the supported CPUs changed. igorm 7395d 01h /dbg_interface/tags/asyst_2
143 Signals for easier debugging removed. igorm 7395d 03h /dbg_interface/tags/asyst_2
142 Typo fixed. igorm 7395d 04h /dbg_interface/tags/asyst_2
141 data_cnt_lim length changed to reduce number of warnings. igorm 7395d 23h /dbg_interface/tags/asyst_2
140 CRC checking of incoming CRC added to all tasks. igorm 7396d 14h /dbg_interface/tags/asyst_2
139 New release of the debug interface (3rd. release). igorm 7398d 17h /dbg_interface/tags/asyst_2
138 Temp version before changing dbg interface. igorm 7404d 21h /dbg_interface/tags/asyst_2
136 Table describing chain codes added. igorm 7408d 22h /dbg_interface/tags/asyst_2
135 'hz changed to 1'hz because Icarus complains. igorm 7411d 21h /dbg_interface/tags/asyst_2
132 Documentation updated. Many missing things added. igorm 7412d 20h /dbg_interface/tags/asyst_2
131 Documentation updated. Many missing things added. igorm 7412d 20h /dbg_interface/tags/asyst_2
129 New documentation. mohor 7454d 19h /dbg_interface/tags/asyst_2
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7457d 03h /dbg_interface/tags/asyst_2
126 run_sim.scr renamed to run_sim for VATS. mohor 7460d 02h /dbg_interface/tags/asyst_2
124 Display for VATS added. mohor 7461d 23h /dbg_interface/tags/asyst_2
123 All flipflops are reset. mohor 7461d 23h /dbg_interface/tags/asyst_2
121 Port signals are all set to zero after reset. mohor 7464d 23h /dbg_interface/tags/asyst_2
120 test stall_test added. mohor 7465d 02h /dbg_interface/tags/asyst_2
119 cpu_stall_o activated as soon as bp occurs. mohor 7465d 03h /dbg_interface/tags/asyst_2
117 Define name changed. mohor 7466d 23h /dbg_interface/tags/asyst_2
116 Data latching changed when testing WB. mohor 7466d 23h /dbg_interface/tags/asyst_2
115 More debug data added. mohor 7467d 03h /dbg_interface/tags/asyst_2
114 CRC generation iand verification in bench changed. mohor 7467d 04h /dbg_interface/tags/asyst_2
113 IDCODE test improved. mohor 7467d 05h /dbg_interface/tags/asyst_2
112 dbg_tb_defines.v not used. mohor 7468d 00h /dbg_interface/tags/asyst_2
111 Define tap_defines.v added to test bench. mohor 7468d 00h /dbg_interface/tags/asyst_2
110 Waiting for "ready" improved. mohor 7468d 01h /dbg_interface/tags/asyst_2

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