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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl/] - Rev 95

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Rev Log message Author Age Path
95 Temp version. mohor 7484d 23h /dbg_interface/tags/asyst_2/rtl
94 temp version. Resets will be changed in next version. mohor 7485d 09h /dbg_interface/tags/asyst_2/rtl
93 tmp version. mohor 7486d 10h /dbg_interface/tags/asyst_2/rtl
92 temp version. mohor 7489d 14h /dbg_interface/tags/asyst_2/rtl
91 tmp version. mohor 7490d 09h /dbg_interface/tags/asyst_2/rtl
90 tmp version. mohor 7491d 04h /dbg_interface/tags/asyst_2/rtl
89 temp4 version. mohor 7492d 10h /dbg_interface/tags/asyst_2/rtl
88 temp3 version. mohor 7493d 05h /dbg_interface/tags/asyst_2/rtl
87 tmp2 version. mohor 7494d 10h /dbg_interface/tags/asyst_2/rtl
86 Tmp version. mohor 7507d 06h /dbg_interface/tags/asyst_2/rtl
83 Small fix. mohor 7507d 06h /dbg_interface/tags/asyst_2/rtl
82 New directory structure. New version of the debug interface. mohor 7507d 07h /dbg_interface/tags/asyst_2/rtl
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7507d 07h /dbg_interface/tags/asyst_2/rtl
77 MBIST chain connection fixed. mohor 7568d 04h /dbg_interface/tags/asyst_2/rtl
73 CRC logic changed. mohor 7568d 06h /dbg_interface/tags/asyst_2/rtl
71 Mbist support added. simons 7570d 12h /dbg_interface/tags/asyst_2/rtl
67 Lower two address lines must be always zero. simons 7603d 08h /dbg_interface/tags/asyst_2/rtl
65 WB_CNTL register added, some syncronization fixes. simons 7604d 07h /dbg_interface/tags/asyst_2/rtl
63 Three more chains added for cpu debug access. simons 7624d 08h /dbg_interface/tags/asyst_2/rtl
61 Lapsus fixed. simons 7652d 08h /dbg_interface/tags/asyst_2/rtl
59 Reset value for riscsel register set to 1. simons 7652d 08h /dbg_interface/tags/asyst_2/rtl
57 Multiple cpu support added. simons 7652d 10h /dbg_interface/tags/asyst_2/rtl
53 Trst active high. Inverted on higher layer. mohor 7919d 07h /dbg_interface/tags/asyst_2/rtl
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7919d 08h /dbg_interface/tags/asyst_2/rtl
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7946d 19h /dbg_interface/tags/asyst_2/rtl
47 mon_cntl_o signals that controls monitor mux added. mohor 8102d 07h /dbg_interface/tags/asyst_2/rtl
46 Asynchronous reset used instead of synchronous. mohor 8110d 13h /dbg_interface/tags/asyst_2/rtl
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8117d 09h /dbg_interface/tags/asyst_2/rtl
44 Signal names changed to lower case. mohor 8117d 09h /dbg_interface/tags/asyst_2/rtl
43 Intentional error removed. mohor 8122d 09h /dbg_interface/tags/asyst_2/rtl

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