OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [asyst_2/] [rtl] - Rev 102

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
102 New version. mohor 7497d 20h /dbg_interface/tags/asyst_2/rtl
101 Almost finished. mohor 7497d 21h /dbg_interface/tags/asyst_2/rtl
100 *** empty log message *** mohor 7499d 00h /dbg_interface/tags/asyst_2/rtl
99 cpu registers added. mohor 7499d 00h /dbg_interface/tags/asyst_2/rtl
97 Working. mohor 7500d 02h /dbg_interface/tags/asyst_2/rtl
95 Temp version. mohor 7500d 15h /dbg_interface/tags/asyst_2/rtl
94 temp version. Resets will be changed in next version. mohor 7501d 02h /dbg_interface/tags/asyst_2/rtl
93 tmp version. mohor 7502d 03h /dbg_interface/tags/asyst_2/rtl
92 temp version. mohor 7505d 07h /dbg_interface/tags/asyst_2/rtl
91 tmp version. mohor 7506d 02h /dbg_interface/tags/asyst_2/rtl
90 tmp version. mohor 7506d 21h /dbg_interface/tags/asyst_2/rtl
89 temp4 version. mohor 7508d 02h /dbg_interface/tags/asyst_2/rtl
88 temp3 version. mohor 7508d 21h /dbg_interface/tags/asyst_2/rtl
87 tmp2 version. mohor 7510d 02h /dbg_interface/tags/asyst_2/rtl
86 Tmp version. mohor 7522d 22h /dbg_interface/tags/asyst_2/rtl
83 Small fix. mohor 7522d 23h /dbg_interface/tags/asyst_2/rtl
82 New directory structure. New version of the debug interface. mohor 7522d 23h /dbg_interface/tags/asyst_2/rtl
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7522d 23h /dbg_interface/tags/asyst_2/rtl
77 MBIST chain connection fixed. mohor 7583d 20h /dbg_interface/tags/asyst_2/rtl
73 CRC logic changed. mohor 7583d 22h /dbg_interface/tags/asyst_2/rtl
71 Mbist support added. simons 7586d 05h /dbg_interface/tags/asyst_2/rtl
67 Lower two address lines must be always zero. simons 7619d 00h /dbg_interface/tags/asyst_2/rtl
65 WB_CNTL register added, some syncronization fixes. simons 7620d 00h /dbg_interface/tags/asyst_2/rtl
63 Three more chains added for cpu debug access. simons 7640d 00h /dbg_interface/tags/asyst_2/rtl
61 Lapsus fixed. simons 7668d 00h /dbg_interface/tags/asyst_2/rtl
59 Reset value for riscsel register set to 1. simons 7668d 01h /dbg_interface/tags/asyst_2/rtl
57 Multiple cpu support added. simons 7668d 02h /dbg_interface/tags/asyst_2/rtl
53 Trst active high. Inverted on higher layer. mohor 7935d 00h /dbg_interface/tags/asyst_2/rtl
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7935d 00h /dbg_interface/tags/asyst_2/rtl
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7962d 12h /dbg_interface/tags/asyst_2/rtl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.