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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl] - Rev 121

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Rev Log message Author Age Path
121 Port signals are all set to zero after reset. mohor 7477d 11h /dbg_interface/tags/asyst_2/rtl
119 cpu_stall_o activated as soon as bp occurs. mohor 7477d 14h /dbg_interface/tags/asyst_2/rtl
117 Define name changed. mohor 7479d 10h /dbg_interface/tags/asyst_2/rtl
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7480d 17h /dbg_interface/tags/asyst_2/rtl
106 Sensitivity list updated. simons 7481d 15h /dbg_interface/tags/asyst_2/rtl
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7482d 06h /dbg_interface/tags/asyst_2/rtl
102 New version. mohor 7482d 07h /dbg_interface/tags/asyst_2/rtl
101 Almost finished. mohor 7482d 08h /dbg_interface/tags/asyst_2/rtl
100 *** empty log message *** mohor 7483d 10h /dbg_interface/tags/asyst_2/rtl
99 cpu registers added. mohor 7483d 10h /dbg_interface/tags/asyst_2/rtl
97 Working. mohor 7484d 12h /dbg_interface/tags/asyst_2/rtl
95 Temp version. mohor 7485d 02h /dbg_interface/tags/asyst_2/rtl
94 temp version. Resets will be changed in next version. mohor 7485d 12h /dbg_interface/tags/asyst_2/rtl
93 tmp version. mohor 7486d 13h /dbg_interface/tags/asyst_2/rtl
92 temp version. mohor 7489d 17h /dbg_interface/tags/asyst_2/rtl
91 tmp version. mohor 7490d 12h /dbg_interface/tags/asyst_2/rtl
90 tmp version. mohor 7491d 07h /dbg_interface/tags/asyst_2/rtl
89 temp4 version. mohor 7492d 13h /dbg_interface/tags/asyst_2/rtl
88 temp3 version. mohor 7493d 07h /dbg_interface/tags/asyst_2/rtl
87 tmp2 version. mohor 7494d 12h /dbg_interface/tags/asyst_2/rtl
86 Tmp version. mohor 7507d 08h /dbg_interface/tags/asyst_2/rtl
83 Small fix. mohor 7507d 09h /dbg_interface/tags/asyst_2/rtl
82 New directory structure. New version of the debug interface. mohor 7507d 09h /dbg_interface/tags/asyst_2/rtl
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7507d 09h /dbg_interface/tags/asyst_2/rtl
77 MBIST chain connection fixed. mohor 7568d 06h /dbg_interface/tags/asyst_2/rtl
73 CRC logic changed. mohor 7568d 08h /dbg_interface/tags/asyst_2/rtl
71 Mbist support added. simons 7570d 15h /dbg_interface/tags/asyst_2/rtl
67 Lower two address lines must be always zero. simons 7603d 11h /dbg_interface/tags/asyst_2/rtl
65 WB_CNTL register added, some syncronization fixes. simons 7604d 10h /dbg_interface/tags/asyst_2/rtl
63 Three more chains added for cpu debug access. simons 7624d 11h /dbg_interface/tags/asyst_2/rtl

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