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[/] [dbg_interface/] [tags/] [asyst_2/] [rtl] - Rev 46

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Rev Log message Author Age Path
46 Asynchronous reset used instead of synchronous. mohor 8098d 10h /dbg_interface/tags/asyst_2/rtl
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8105d 06h /dbg_interface/tags/asyst_2/rtl
44 Signal names changed to lower case. mohor 8105d 06h /dbg_interface/tags/asyst_2/rtl
43 Intentional error removed. mohor 8110d 06h /dbg_interface/tags/asyst_2/rtl
42 A block for checking possible simulation/synthesis missmatch added. mohor 8110d 08h /dbg_interface/tags/asyst_2/rtl
41 Function changed to logic because of some synthesis warnings. mohor 8118d 05h /dbg_interface/tags/asyst_2/rtl
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8132d 04h /dbg_interface/tags/asyst_2/rtl
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8133d 06h /dbg_interface/tags/asyst_2/rtl
38 Few outputs for boundary scan chain added. mohor 8146d 04h /dbg_interface/tags/asyst_2/rtl
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8146d 08h /dbg_interface/tags/asyst_2/rtl
36 Structure changed. Hooks for jtag chain added. mohor 8150d 03h /dbg_interface/tags/asyst_2/rtl
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8180d 06h /dbg_interface/tags/asyst_2/rtl
32 Stupid bug that was entered by previous update fixed. mohor 8181d 05h /dbg_interface/tags/asyst_2/rtl
31 trst synchronization is not needed and was removed. mohor 8181d 06h /dbg_interface/tags/asyst_2/rtl
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8192d 11h /dbg_interface/tags/asyst_2/rtl
28 TDO and TDO Enable signal are separated into two signals. mohor 8228d 08h /dbg_interface/tags/asyst_2/rtl
27 Warnings from synthesys tools fixed. mohor 8242d 09h /dbg_interface/tags/asyst_2/rtl
26 Warnings from synthesys tools fixed. mohor 8242d 09h /dbg_interface/tags/asyst_2/rtl
25 trst signal is synchronized to wb_clk_i. mohor 8243d 05h /dbg_interface/tags/asyst_2/rtl
23 Trace disabled by default. mohor 8250d 09h /dbg_interface/tags/asyst_2/rtl
22 Register length fixed. mohor 8250d 09h /dbg_interface/tags/asyst_2/rtl
21 CRC is returned when chain selection data is transmitted. mohor 8251d 05h /dbg_interface/tags/asyst_2/rtl
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8252d 08h /dbg_interface/tags/asyst_2/rtl
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8264d 09h /dbg_interface/tags/asyst_2/rtl
18 Reset signals are not combined any more. mohor 8266d 18h /dbg_interface/tags/asyst_2/rtl
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8290d 07h /dbg_interface/tags/asyst_2/rtl
15 bs_chain_o added. mohor 8292d 08h /dbg_interface/tags/asyst_2/rtl
13 Signal names changed to lowercase. mohor 8293d 09h /dbg_interface/tags/asyst_2/rtl
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8294d 09h /dbg_interface/tags/asyst_2/rtl
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8315d 05h /dbg_interface/tags/asyst_2/rtl

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