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[/] [dbg_interface/] [tags/] [highland_ver1/] [bench/] [verilog/] [dbg_tb.v] - Rev 158

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158 root 5590d 03h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
133 This commit was manufactured by cvs2svn to create tag 'highland_ver1'. 7412d 05h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7456d 13h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
124 Display for VATS added. mohor 7461d 09h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
121 Port signals are all set to zero after reset. mohor 7464d 09h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
120 test stall_test added. mohor 7464d 12h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
117 Define name changed. mohor 7466d 09h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
116 Data latching changed when testing WB. mohor 7466d 09h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
115 More debug data added. mohor 7466d 13h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
114 CRC generation iand verification in bench changed. mohor 7466d 14h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
113 IDCODE test improved. mohor 7466d 15h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
111 Define tap_defines.v added to test bench. mohor 7467d 10h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
110 Waiting for "ready" improved. mohor 7467d 10h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
102 New version. mohor 7469d 05h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
101 Almost finished. mohor 7469d 06h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
99 cpu registers added. mohor 7470d 08h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
96 Working. mohor 7471d 12h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
95 Temp version. mohor 7472d 00h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
93 tmp version. mohor 7473d 11h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
92 temp version. mohor 7476d 15h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
91 tmp version. mohor 7477d 10h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
90 tmp version. mohor 7478d 05h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
89 temp4 version. mohor 7479d 11h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
88 temp3 version. mohor 7480d 06h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
87 tmp2 version. mohor 7481d 11h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
80 New version of the debug interface. Not finished, yet. mohor 7494d 08h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
73 CRC logic changed. mohor 7555d 07h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
63 Three more chains added for cpu debug access. simons 7611d 09h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8089d 08h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v
38 Few outputs for boundary scan chain added. mohor 8145d 08h /dbg_interface/tags/highland_ver1/bench/verilog/dbg_tb.v

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