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[/] [dbg_interface/] [tags/] [highland_ver1/] [bench] - Rev 113

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Rev Log message Author Age Path
113 IDCODE test improved. mohor 7506d 18h /dbg_interface/tags/highland_ver1/bench
112 dbg_tb_defines.v not used. mohor 7507d 13h /dbg_interface/tags/highland_ver1/bench
111 Define tap_defines.v added to test bench. mohor 7507d 13h /dbg_interface/tags/highland_ver1/bench
110 Waiting for "ready" improved. mohor 7507d 13h /dbg_interface/tags/highland_ver1/bench
102 New version. mohor 7509d 08h /dbg_interface/tags/highland_ver1/bench
101 Almost finished. mohor 7509d 09h /dbg_interface/tags/highland_ver1/bench
99 cpu registers added. mohor 7510d 11h /dbg_interface/tags/highland_ver1/bench
96 Working. mohor 7511d 15h /dbg_interface/tags/highland_ver1/bench
95 Temp version. mohor 7512d 03h /dbg_interface/tags/highland_ver1/bench
93 tmp version. mohor 7513d 15h /dbg_interface/tags/highland_ver1/bench
92 temp version. mohor 7516d 18h /dbg_interface/tags/highland_ver1/bench
91 tmp version. mohor 7517d 13h /dbg_interface/tags/highland_ver1/bench
90 tmp version. mohor 7518d 08h /dbg_interface/tags/highland_ver1/bench
89 temp4 version. mohor 7519d 14h /dbg_interface/tags/highland_ver1/bench
88 temp3 version. mohor 7520d 09h /dbg_interface/tags/highland_ver1/bench
87 tmp2 version. mohor 7521d 14h /dbg_interface/tags/highland_ver1/bench
80 New version of the debug interface. Not finished, yet. mohor 7534d 12h /dbg_interface/tags/highland_ver1/bench
75 Simulation files. mohor 7595d 09h /dbg_interface/tags/highland_ver1/bench
73 CRC logic changed. mohor 7595d 10h /dbg_interface/tags/highland_ver1/bench
63 Three more chains added for cpu debug access. simons 7651d 12h /dbg_interface/tags/highland_ver1/bench
47 mon_cntl_o signals that controls monitor mux added. mohor 8129d 11h /dbg_interface/tags/highland_ver1/bench
38 Few outputs for boundary scan chain added. mohor 8185d 11h /dbg_interface/tags/highland_ver1/bench
36 Structure changed. Hooks for jtag chain added. mohor 8189d 11h /dbg_interface/tags/highland_ver1/bench
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8329d 14h /dbg_interface/tags/highland_ver1/bench
15 bs_chain_o added. mohor 8331d 15h /dbg_interface/tags/highland_ver1/bench
13 Signal names changed to lowercase. mohor 8332d 16h /dbg_interface/tags/highland_ver1/bench
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.
mohor 8333d 16h /dbg_interface/tags/highland_ver1/bench
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8354d 12h /dbg_interface/tags/highland_ver1/bench
9 Working version. Few bugs fixed, comments added. mohor 8358d 16h /dbg_interface/tags/highland_ver1/bench
6 Minor changes for simulation. mohor 8359d 14h /dbg_interface/tags/highland_ver1/bench

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