URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5589d 15h	/dbg_interface/tags/rel_15/rtl
109	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7467d 03h	/dbg_interface/tags/rel_15/rtl
108	Reset values width added because of FV, a good sentence changed because some tools can not handle it.	simons	7467d 03h	/dbg_interface/tags/rel_15/rtl
106	Sensitivity list updated.	simons	7468d 02h	/dbg_interface/tags/rel_15/rtl
104	cpu_tall_o is set with cpu_stb_o or register.	mohor	7468d 16h	/dbg_interface/tags/rel_15/rtl
102	New version.	mohor	7468d 17h	/dbg_interface/tags/rel_15/rtl
101	Almost finished.	mohor	7468d 18h	/dbg_interface/tags/rel_15/rtl
100	* empty log message *	mohor	7469d 20h	/dbg_interface/tags/rel_15/rtl
99	cpu registers added.	mohor	7469d 20h	/dbg_interface/tags/rel_15/rtl
97	Working.	mohor	7470d 23h	/dbg_interface/tags/rel_15/rtl
95	Temp version.	mohor	7471d 12h	/dbg_interface/tags/rel_15/rtl
94	temp version. Resets will be changed in next version.	mohor	7471d 22h	/dbg_interface/tags/rel_15/rtl
93	tmp version.	mohor	7472d 23h	/dbg_interface/tags/rel_15/rtl
92	temp version.	mohor	7476d 03h	/dbg_interface/tags/rel_15/rtl
91	tmp version.	mohor	7476d 22h	/dbg_interface/tags/rel_15/rtl
90	tmp version.	mohor	7477d 17h	/dbg_interface/tags/rel_15/rtl
89	temp4 version.	mohor	7478d 23h	/dbg_interface/tags/rel_15/rtl
88	temp3 version.	mohor	7479d 18h	/dbg_interface/tags/rel_15/rtl
87	tmp2 version.	mohor	7480d 23h	/dbg_interface/tags/rel_15/rtl
86	Tmp version.	mohor	7493d 19h	/dbg_interface/tags/rel_15/rtl
83	Small fix.	mohor	7493d 20h	/dbg_interface/tags/rel_15/rtl
82	New directory structure. New version of the debug interface.	mohor	7493d 20h	/dbg_interface/tags/rel_15/rtl
81	New directory structure. New version of the debug interface. Files that are not needed removed.	mohor	7493d 20h	/dbg_interface/tags/rel_15/rtl
77	MBIST chain connection fixed.	mohor	7554d 17h	/dbg_interface/tags/rel_15/rtl
73	CRC logic changed.	mohor	7554d 19h	/dbg_interface/tags/rel_15/rtl
71	Mbist support added.	simons	7557d 01h	/dbg_interface/tags/rel_15/rtl
67	Lower two address lines must be always zero.	simons	7589d 21h	/dbg_interface/tags/rel_15/rtl
65	WB_CNTL register added, some syncronization fixes.	simons	7590d 20h	/dbg_interface/tags/rel_15/rtl
63	Three more chains added for cpu debug access.	simons	7610d 21h	/dbg_interface/tags/rel_15/rtl
61	Lapsus fixed.	simons	7638d 21h	/dbg_interface/tags/rel_15/rtl

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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] - Rev 158

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