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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5637d 03h /dbg_interface/tags/rel_15/rtl/verilog
109 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7514d 16h /dbg_interface/tags/rel_15/rtl/verilog
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7514d 16h /dbg_interface/tags/rel_15/rtl/verilog
106 Sensitivity list updated. simons 7515d 14h /dbg_interface/tags/rel_15/rtl/verilog
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7516d 05h /dbg_interface/tags/rel_15/rtl/verilog
102 New version. mohor 7516d 05h /dbg_interface/tags/rel_15/rtl/verilog
101 Almost finished. mohor 7516d 06h /dbg_interface/tags/rel_15/rtl/verilog
100 *** empty log message *** mohor 7517d 08h /dbg_interface/tags/rel_15/rtl/verilog
99 cpu registers added. mohor 7517d 08h /dbg_interface/tags/rel_15/rtl/verilog
97 Working. mohor 7518d 11h /dbg_interface/tags/rel_15/rtl/verilog
95 Temp version. mohor 7519d 00h /dbg_interface/tags/rel_15/rtl/verilog
94 temp version. Resets will be changed in next version. mohor 7519d 11h /dbg_interface/tags/rel_15/rtl/verilog
93 tmp version. mohor 7520d 12h /dbg_interface/tags/rel_15/rtl/verilog
92 temp version. mohor 7523d 16h /dbg_interface/tags/rel_15/rtl/verilog
91 tmp version. mohor 7524d 11h /dbg_interface/tags/rel_15/rtl/verilog
90 tmp version. mohor 7525d 05h /dbg_interface/tags/rel_15/rtl/verilog
89 temp4 version. mohor 7526d 11h /dbg_interface/tags/rel_15/rtl/verilog
88 temp3 version. mohor 7527d 06h /dbg_interface/tags/rel_15/rtl/verilog
87 tmp2 version. mohor 7528d 11h /dbg_interface/tags/rel_15/rtl/verilog
86 Tmp version. mohor 7541d 07h /dbg_interface/tags/rel_15/rtl/verilog
83 Small fix. mohor 7541d 08h /dbg_interface/tags/rel_15/rtl/verilog
82 New directory structure. New version of the debug interface. mohor 7541d 08h /dbg_interface/tags/rel_15/rtl/verilog
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7541d 08h /dbg_interface/tags/rel_15/rtl/verilog
77 MBIST chain connection fixed. mohor 7602d 05h /dbg_interface/tags/rel_15/rtl/verilog
73 CRC logic changed. mohor 7602d 07h /dbg_interface/tags/rel_15/rtl/verilog
71 Mbist support added. simons 7604d 14h /dbg_interface/tags/rel_15/rtl/verilog
67 Lower two address lines must be always zero. simons 7637d 09h /dbg_interface/tags/rel_15/rtl/verilog
65 WB_CNTL register added, some syncronization fixes. simons 7638d 09h /dbg_interface/tags/rel_15/rtl/verilog
63 Three more chains added for cpu debug access. simons 7658d 09h /dbg_interface/tags/rel_15/rtl/verilog
61 Lapsus fixed. simons 7686d 09h /dbg_interface/tags/rel_15/rtl/verilog

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