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[/] [dbg_interface/] [tags/] [rel_15/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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Rev Log message Author Age Path
158 root 5589d 07h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
109 This commit was manufactured by cvs2svn to create tag 'rel_15'. 7466d 20h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7466d 20h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
106 Sensitivity list updated. simons 7467d 18h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
101 Almost finished. mohor 7468d 10h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
99 cpu registers added. mohor 7469d 12h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
95 Temp version. mohor 7471d 04h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7493d 12h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
73 CRC logic changed. mohor 7554d 11h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
67 Lower two address lines must be always zero. simons 7589d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
65 WB_CNTL register added, some syncronization fixes. simons 7590d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
63 Three more chains added for cpu debug access. simons 7610d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
57 Multiple cpu support added. simons 7638d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7905d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7933d 01h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8088d 13h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
44 Signal names changed to lower case. mohor 8103d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
43 Intentional error removed. mohor 8108d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
42 A block for checking possible simulation/synthesis missmatch added. mohor 8108d 16h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8144d 17h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
36 Structure changed. Hooks for jtag chain added. mohor 8148d 12h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8178d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
32 Stupid bug that was entered by previous update fixed. mohor 8179d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
31 trst synchronization is not needed and was removed. mohor 8179d 15h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8190d 19h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
28 TDO and TDO Enable signal are separated into two signals. mohor 8226d 16h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
25 trst signal is synchronized to wb_clk_i. mohor 8241d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
22 Register length fixed. mohor 8248d 18h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
21 CRC is returned when chain selection data is transmitted. mohor 8249d 14h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8250d 16h /dbg_interface/tags/rel_15/rtl/verilog/dbg_top.v

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