URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19/] [bench/] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5595d 18h	/dbg_interface/tags/rel_19/bench
127	This commit was manufactured by cvs2svn to create tag 'rel_19'.		7465d 03h	/dbg_interface/tags/rel_19/bench
124	Display for VATS added.	mohor	7467d 00h	/dbg_interface/tags/rel_19/bench
121	Port signals are all set to zero after reset.	mohor	7470d 00h	/dbg_interface/tags/rel_19/bench
120	test stall_test added.	mohor	7470d 03h	/dbg_interface/tags/rel_19/bench
117	Define name changed.	mohor	7471d 23h	/dbg_interface/tags/rel_19/bench
116	Data latching changed when testing WB.	mohor	7472d 00h	/dbg_interface/tags/rel_19/bench
115	More debug data added.	mohor	7472d 03h	/dbg_interface/tags/rel_19/bench
114	CRC generation iand verification in bench changed.	mohor	7472d 05h	/dbg_interface/tags/rel_19/bench
113	IDCODE test improved.	mohor	7472d 06h	/dbg_interface/tags/rel_19/bench
112	dbg_tb_defines.v not used.	mohor	7473d 00h	/dbg_interface/tags/rel_19/bench
111	Define tap_defines.v added to test bench.	mohor	7473d 00h	/dbg_interface/tags/rel_19/bench
110	Waiting for "ready" improved.	mohor	7473d 01h	/dbg_interface/tags/rel_19/bench
102	New version.	mohor	7474d 20h	/dbg_interface/tags/rel_19/bench
101	Almost finished.	mohor	7474d 21h	/dbg_interface/tags/rel_19/bench
99	cpu registers added.	mohor	7475d 23h	/dbg_interface/tags/rel_19/bench
96	Working.	mohor	7477d 03h	/dbg_interface/tags/rel_19/bench
95	Temp version.	mohor	7477d 15h	/dbg_interface/tags/rel_19/bench
93	tmp version.	mohor	7479d 02h	/dbg_interface/tags/rel_19/bench
92	temp version.	mohor	7482d 06h	/dbg_interface/tags/rel_19/bench
91	tmp version.	mohor	7483d 01h	/dbg_interface/tags/rel_19/bench
90	tmp version.	mohor	7483d 20h	/dbg_interface/tags/rel_19/bench
89	temp4 version.	mohor	7485d 02h	/dbg_interface/tags/rel_19/bench
88	temp3 version.	mohor	7485d 20h	/dbg_interface/tags/rel_19/bench
87	tmp2 version.	mohor	7487d 01h	/dbg_interface/tags/rel_19/bench
80	New version of the debug interface. Not finished, yet.	mohor	7499d 23h	/dbg_interface/tags/rel_19/bench
75	Simulation files.	mohor	7560d 21h	/dbg_interface/tags/rel_19/bench
73	CRC logic changed.	mohor	7560d 21h	/dbg_interface/tags/rel_19/bench
63	Three more chains added for cpu debug access.	simons	7617d 00h	/dbg_interface/tags/rel_19/bench
47	mon_cntl_o signals that controls monitor mux added.	mohor	8094d 23h	/dbg_interface/tags/rel_19/bench

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[/] [dbg_interface/] [tags/] [rel_19/] [bench/] - Rev 158

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