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[/] [dbg_interface/] [tags/] [rel_19/] [bench/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5630d 22h /dbg_interface/tags/rel_19/bench/verilog
127 This commit was manufactured by cvs2svn to create tag 'rel_19'. 7500d 07h /dbg_interface/tags/rel_19/bench/verilog
124 Display for VATS added. mohor 7502d 04h /dbg_interface/tags/rel_19/bench/verilog
121 Port signals are all set to zero after reset. mohor 7505d 04h /dbg_interface/tags/rel_19/bench/verilog
120 test stall_test added. mohor 7505d 07h /dbg_interface/tags/rel_19/bench/verilog
117 Define name changed. mohor 7507d 04h /dbg_interface/tags/rel_19/bench/verilog
116 Data latching changed when testing WB. mohor 7507d 04h /dbg_interface/tags/rel_19/bench/verilog
115 More debug data added. mohor 7507d 08h /dbg_interface/tags/rel_19/bench/verilog
114 CRC generation iand verification in bench changed. mohor 7507d 09h /dbg_interface/tags/rel_19/bench/verilog
113 IDCODE test improved. mohor 7507d 10h /dbg_interface/tags/rel_19/bench/verilog
112 dbg_tb_defines.v not used. mohor 7508d 05h /dbg_interface/tags/rel_19/bench/verilog
111 Define tap_defines.v added to test bench. mohor 7508d 05h /dbg_interface/tags/rel_19/bench/verilog
110 Waiting for "ready" improved. mohor 7508d 05h /dbg_interface/tags/rel_19/bench/verilog
102 New version. mohor 7510d 00h /dbg_interface/tags/rel_19/bench/verilog
101 Almost finished. mohor 7510d 01h /dbg_interface/tags/rel_19/bench/verilog
99 cpu registers added. mohor 7511d 03h /dbg_interface/tags/rel_19/bench/verilog
96 Working. mohor 7512d 07h /dbg_interface/tags/rel_19/bench/verilog
95 Temp version. mohor 7512d 19h /dbg_interface/tags/rel_19/bench/verilog
93 tmp version. mohor 7514d 06h /dbg_interface/tags/rel_19/bench/verilog
92 temp version. mohor 7517d 10h /dbg_interface/tags/rel_19/bench/verilog
91 tmp version. mohor 7518d 05h /dbg_interface/tags/rel_19/bench/verilog
90 tmp version. mohor 7519d 00h /dbg_interface/tags/rel_19/bench/verilog
89 temp4 version. mohor 7520d 06h /dbg_interface/tags/rel_19/bench/verilog
88 temp3 version. mohor 7521d 01h /dbg_interface/tags/rel_19/bench/verilog
87 tmp2 version. mohor 7522d 06h /dbg_interface/tags/rel_19/bench/verilog
80 New version of the debug interface. Not finished, yet. mohor 7535d 04h /dbg_interface/tags/rel_19/bench/verilog
75 Simulation files. mohor 7596d 01h /dbg_interface/tags/rel_19/bench/verilog
73 CRC logic changed. mohor 7596d 02h /dbg_interface/tags/rel_19/bench/verilog
63 Three more chains added for cpu debug access. simons 7652d 04h /dbg_interface/tags/rel_19/bench/verilog
47 mon_cntl_o signals that controls monitor mux added. mohor 8130d 03h /dbg_interface/tags/rel_19/bench/verilog

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