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[/] [dbg_interface/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 63

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Rev Log message Author Age Path
63 Three more chains added for cpu debug access. simons 7657d 23h /dbg_interface/tags/rel_19/rtl/verilog
61 Lapsus fixed. simons 7685d 23h /dbg_interface/tags/rel_19/rtl/verilog
59 Reset value for riscsel register set to 1. simons 7686d 00h /dbg_interface/tags/rel_19/rtl/verilog
57 Multiple cpu support added. simons 7686d 01h /dbg_interface/tags/rel_19/rtl/verilog
53 Trst active high. Inverted on higher layer. mohor 7952d 23h /dbg_interface/tags/rel_19/rtl/verilog
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7952d 23h /dbg_interface/tags/rel_19/rtl/verilog
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7980d 11h /dbg_interface/tags/rel_19/rtl/verilog
47 mon_cntl_o signals that controls monitor mux added. mohor 8135d 23h /dbg_interface/tags/rel_19/rtl/verilog
46 Asynchronous reset used instead of synchronous. mohor 8144d 05h /dbg_interface/tags/rel_19/rtl/verilog
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8151d 00h /dbg_interface/tags/rel_19/rtl/verilog
44 Signal names changed to lower case. mohor 8151d 00h /dbg_interface/tags/rel_19/rtl/verilog
43 Intentional error removed. mohor 8156d 00h /dbg_interface/tags/rel_19/rtl/verilog
42 A block for checking possible simulation/synthesis missmatch added. mohor 8156d 02h /dbg_interface/tags/rel_19/rtl/verilog
41 Function changed to logic because of some synthesis warnings. mohor 8163d 23h /dbg_interface/tags/rel_19/rtl/verilog
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8177d 23h /dbg_interface/tags/rel_19/rtl/verilog
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8179d 00h /dbg_interface/tags/rel_19/rtl/verilog
38 Few outputs for boundary scan chain added. mohor 8191d 23h /dbg_interface/tags/rel_19/rtl/verilog
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8192d 03h /dbg_interface/tags/rel_19/rtl/verilog
36 Structure changed. Hooks for jtag chain added. mohor 8195d 22h /dbg_interface/tags/rel_19/rtl/verilog
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8226d 01h /dbg_interface/tags/rel_19/rtl/verilog
32 Stupid bug that was entered by previous update fixed. mohor 8227d 00h /dbg_interface/tags/rel_19/rtl/verilog
31 trst synchronization is not needed and was removed. mohor 8227d 01h /dbg_interface/tags/rel_19/rtl/verilog
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8238d 05h /dbg_interface/tags/rel_19/rtl/verilog
28 TDO and TDO Enable signal are separated into two signals. mohor 8274d 02h /dbg_interface/tags/rel_19/rtl/verilog
27 Warnings from synthesys tools fixed. mohor 8288d 03h /dbg_interface/tags/rel_19/rtl/verilog
26 Warnings from synthesys tools fixed. mohor 8288d 03h /dbg_interface/tags/rel_19/rtl/verilog
25 trst signal is synchronized to wb_clk_i. mohor 8289d 00h /dbg_interface/tags/rel_19/rtl/verilog
23 Trace disabled by default. mohor 8296d 04h /dbg_interface/tags/rel_19/rtl/verilog
22 Register length fixed. mohor 8296d 04h /dbg_interface/tags/rel_19/rtl/verilog
21 CRC is returned when chain selection data is transmitted. mohor 8297d 00h /dbg_interface/tags/rel_19/rtl/verilog

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