OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_19] - Rev 85

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
85 New directory structure. New debug interface. mohor 7538d 03h /dbg_interface/tags/rel_19
84 Removed files that are not needed any more. mohor 7538d 03h /dbg_interface/tags/rel_19
83 Small fix. mohor 7538d 03h /dbg_interface/tags/rel_19
82 New directory structure. New version of the debug interface. mohor 7538d 03h /dbg_interface/tags/rel_19
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7538d 03h /dbg_interface/tags/rel_19
80 New version of the debug interface. Not finished, yet. mohor 7538d 04h /dbg_interface/tags/rel_19
77 MBIST chain connection fixed. mohor 7599d 00h /dbg_interface/tags/rel_19
75 Simulation files. mohor 7599d 02h /dbg_interface/tags/rel_19
74 Removed. mohor 7599d 02h /dbg_interface/tags/rel_19
73 CRC logic changed. mohor 7599d 02h /dbg_interface/tags/rel_19
71 Mbist support added. simons 7601d 09h /dbg_interface/tags/rel_19
70 A pdf copy of existing doc document. simons 7608d 10h /dbg_interface/tags/rel_19
69 WBCNTL added, multiple CPU support described. simons 7629d 00h /dbg_interface/tags/rel_19
67 Lower two address lines must be always zero. simons 7634d 04h /dbg_interface/tags/rel_19
65 WB_CNTL register added, some syncronization fixes. simons 7635d 04h /dbg_interface/tags/rel_19
63 Three more chains added for cpu debug access. simons 7655d 05h /dbg_interface/tags/rel_19
61 Lapsus fixed. simons 7683d 04h /dbg_interface/tags/rel_19
59 Reset value for riscsel register set to 1. simons 7683d 05h /dbg_interface/tags/rel_19
57 Multiple cpu support added. simons 7683d 06h /dbg_interface/tags/rel_19
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7950d 02h /dbg_interface/tags/rel_19
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7950d 03h /dbg_interface/tags/rel_19
53 Trst active high. Inverted on higher layer. mohor 7950d 04h /dbg_interface/tags/rel_19
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7950d 04h /dbg_interface/tags/rel_19
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7977d 16h /dbg_interface/tags/rel_19
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7977d 16h /dbg_interface/tags/rel_19
47 mon_cntl_o signals that controls monitor mux added. mohor 8133d 04h /dbg_interface/tags/rel_19
46 Asynchronous reset used instead of synchronous. mohor 8141d 10h /dbg_interface/tags/rel_19
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8148d 06h /dbg_interface/tags/rel_19
44 Signal names changed to lower case. mohor 8148d 06h /dbg_interface/tags/rel_19
43 Intentional error removed. mohor 8153d 05h /dbg_interface/tags/rel_19

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.