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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] - Rev 158

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158 root 5624d 03h /dbg_interface/tags/rel_21/bench/verilog
134 This commit was manufactured by cvs2svn to create tag 'rel_21'. 7446d 05h /dbg_interface/tags/rel_21/bench/verilog
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7490d 12h /dbg_interface/tags/rel_21/bench/verilog
124 Display for VATS added. mohor 7495d 08h /dbg_interface/tags/rel_21/bench/verilog
121 Port signals are all set to zero after reset. mohor 7498d 09h /dbg_interface/tags/rel_21/bench/verilog
120 test stall_test added. mohor 7498d 12h /dbg_interface/tags/rel_21/bench/verilog
117 Define name changed. mohor 7500d 08h /dbg_interface/tags/rel_21/bench/verilog
116 Data latching changed when testing WB. mohor 7500d 09h /dbg_interface/tags/rel_21/bench/verilog
115 More debug data added. mohor 7500d 12h /dbg_interface/tags/rel_21/bench/verilog
114 CRC generation iand verification in bench changed. mohor 7500d 14h /dbg_interface/tags/rel_21/bench/verilog
113 IDCODE test improved. mohor 7500d 15h /dbg_interface/tags/rel_21/bench/verilog
112 dbg_tb_defines.v not used. mohor 7501d 09h /dbg_interface/tags/rel_21/bench/verilog
111 Define tap_defines.v added to test bench. mohor 7501d 09h /dbg_interface/tags/rel_21/bench/verilog
110 Waiting for "ready" improved. mohor 7501d 10h /dbg_interface/tags/rel_21/bench/verilog
102 New version. mohor 7503d 05h /dbg_interface/tags/rel_21/bench/verilog
101 Almost finished. mohor 7503d 06h /dbg_interface/tags/rel_21/bench/verilog
99 cpu registers added. mohor 7504d 08h /dbg_interface/tags/rel_21/bench/verilog
96 Working. mohor 7505d 12h /dbg_interface/tags/rel_21/bench/verilog
95 Temp version. mohor 7506d 00h /dbg_interface/tags/rel_21/bench/verilog
93 tmp version. mohor 7507d 11h /dbg_interface/tags/rel_21/bench/verilog
92 temp version. mohor 7510d 15h /dbg_interface/tags/rel_21/bench/verilog
91 tmp version. mohor 7511d 10h /dbg_interface/tags/rel_21/bench/verilog
90 tmp version. mohor 7512d 05h /dbg_interface/tags/rel_21/bench/verilog
89 temp4 version. mohor 7513d 11h /dbg_interface/tags/rel_21/bench/verilog
88 temp3 version. mohor 7514d 05h /dbg_interface/tags/rel_21/bench/verilog
87 tmp2 version. mohor 7515d 10h /dbg_interface/tags/rel_21/bench/verilog
80 New version of the debug interface. Not finished, yet. mohor 7528d 08h /dbg_interface/tags/rel_21/bench/verilog
75 Simulation files. mohor 7589d 06h /dbg_interface/tags/rel_21/bench/verilog
73 CRC logic changed. mohor 7589d 06h /dbg_interface/tags/rel_21/bench/verilog
63 Three more chains added for cpu debug access. simons 7645d 09h /dbg_interface/tags/rel_21/bench/verilog

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