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[/] [dbg_interface/] [tags/] [rel_21/] [bench/] [verilog/] [dbg_tb.v] - Rev 121

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121 Port signals are all set to zero after reset. mohor 7481d 10h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
120 test stall_test added. mohor 7481d 13h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
117 Define name changed. mohor 7483d 10h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
116 Data latching changed when testing WB. mohor 7483d 10h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
115 More debug data added. mohor 7483d 14h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
114 CRC generation iand verification in bench changed. mohor 7483d 15h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
113 IDCODE test improved. mohor 7483d 16h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
111 Define tap_defines.v added to test bench. mohor 7484d 11h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
110 Waiting for "ready" improved. mohor 7484d 12h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
102 New version. mohor 7486d 06h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
101 Almost finished. mohor 7486d 07h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
99 cpu registers added. mohor 7487d 10h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
96 Working. mohor 7488d 14h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
95 Temp version. mohor 7489d 01h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
93 tmp version. mohor 7490d 13h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
92 temp version. mohor 7493d 17h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
91 tmp version. mohor 7494d 12h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
90 tmp version. mohor 7495d 07h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
89 temp4 version. mohor 7496d 12h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
88 temp3 version. mohor 7497d 07h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
87 tmp2 version. mohor 7498d 12h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
80 New version of the debug interface. Not finished, yet. mohor 7511d 10h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
73 CRC logic changed. mohor 7572d 08h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
63 Three more chains added for cpu debug access. simons 7628d 11h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8106d 10h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
38 Few outputs for boundary scan chain added. mohor 8162d 10h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
36 Structure changed. Hooks for jtag chain added. mohor 8166d 09h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8306d 13h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
15 bs_chain_o added. mohor 8308d 14h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v
13 Signal names changed to lowercase. mohor 8309d 14h /dbg_interface/tags/rel_21/bench/verilog/dbg_tb.v

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