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[/] [dbg_interface/] [tags/] [rel_22/] - Rev 158

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Rev Log message Author Age Path
158 root 5604d 16h /dbg_interface/tags/rel_22
137 This commit was manufactured by cvs2svn to create tag 'rel_22'. 7422d 20h /tags/rel_22
136 Table describing chain codes added. igorm 7422d 20h /trunk
135 'hz changed to 1'hz because Icarus complains. igorm 7425d 20h /trunk
132 Documentation updated. Many missing things added. igorm 7426d 18h /trunk
131 Documentation updated. Many missing things added. igorm 7426d 19h /trunk
129 New documentation. mohor 7468d 18h /trunk
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7471d 02h /trunk
126 run_sim.scr renamed to run_sim for VATS. mohor 7474d 01h /trunk
124 Display for VATS added. mohor 7475d 22h /trunk
123 All flipflops are reset. mohor 7475d 22h /trunk
121 Port signals are all set to zero after reset. mohor 7478d 22h /trunk
120 test stall_test added. mohor 7479d 01h /trunk
119 cpu_stall_o activated as soon as bp occurs. mohor 7479d 02h /trunk
117 Define name changed. mohor 7480d 22h /trunk
116 Data latching changed when testing WB. mohor 7480d 22h /trunk
115 More debug data added. mohor 7481d 02h /trunk
114 CRC generation iand verification in bench changed. mohor 7481d 03h /trunk
113 IDCODE test improved. mohor 7481d 04h /trunk
112 dbg_tb_defines.v not used. mohor 7481d 23h /trunk
111 Define tap_defines.v added to test bench. mohor 7481d 23h /trunk
110 Waiting for "ready" improved. mohor 7481d 23h /trunk
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7482d 04h /trunk
106 Sensitivity list updated. simons 7483d 03h /trunk
104 cpu_tall_o is set with cpu_stb_o or register. mohor 7483d 17h /trunk
102 New version. mohor 7483d 18h /trunk
101 Almost finished. mohor 7483d 19h /trunk
100 *** empty log message *** mohor 7484d 21h /trunk
99 cpu registers added. mohor 7484d 21h /trunk
97 Working. mohor 7486d 00h /trunk

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