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[/] [dbg_interface/] [tags/] [rel_22/] - Rev 83

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Rev Log message Author Age Path
83 Small fix. mohor 7537d 14h /dbg_interface/tags/rel_22
82 New directory structure. New version of the debug interface. mohor 7537d 14h /dbg_interface/tags/rel_22
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7537d 14h /dbg_interface/tags/rel_22
80 New version of the debug interface. Not finished, yet. mohor 7537d 15h /dbg_interface/tags/rel_22
77 MBIST chain connection fixed. mohor 7598d 11h /dbg_interface/tags/rel_22
75 Simulation files. mohor 7598d 13h /dbg_interface/tags/rel_22
74 Removed. mohor 7598d 13h /dbg_interface/tags/rel_22
73 CRC logic changed. mohor 7598d 13h /dbg_interface/tags/rel_22
71 Mbist support added. simons 7600d 20h /dbg_interface/tags/rel_22
70 A pdf copy of existing doc document. simons 7607d 21h /dbg_interface/tags/rel_22
69 WBCNTL added, multiple CPU support described. simons 7628d 11h /dbg_interface/tags/rel_22
67 Lower two address lines must be always zero. simons 7633d 15h /dbg_interface/tags/rel_22
65 WB_CNTL register added, some syncronization fixes. simons 7634d 15h /dbg_interface/tags/rel_22
63 Three more chains added for cpu debug access. simons 7654d 16h /dbg_interface/tags/rel_22
61 Lapsus fixed. simons 7682d 15h /dbg_interface/tags/rel_22
59 Reset value for riscsel register set to 1. simons 7682d 16h /dbg_interface/tags/rel_22
57 Multiple cpu support added. simons 7682d 17h /dbg_interface/tags/rel_22
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7949d 13h /dbg_interface/tags/rel_22
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7949d 14h /dbg_interface/tags/rel_22
53 Trst active high. Inverted on higher layer. mohor 7949d 15h /dbg_interface/tags/rel_22
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7949d 15h /dbg_interface/tags/rel_22
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7977d 03h /dbg_interface/tags/rel_22
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7977d 03h /dbg_interface/tags/rel_22
47 mon_cntl_o signals that controls monitor mux added. mohor 8132d 15h /dbg_interface/tags/rel_22
46 Asynchronous reset used instead of synchronous. mohor 8140d 21h /dbg_interface/tags/rel_22
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8147d 17h /dbg_interface/tags/rel_22
44 Signal names changed to lower case. mohor 8147d 17h /dbg_interface/tags/rel_22
43 Intentional error removed. mohor 8152d 16h /dbg_interface/tags/rel_22
42 A block for checking possible simulation/synthesis missmatch added. mohor 8152d 18h /dbg_interface/tags/rel_22
41 Function changed to logic because of some synthesis warnings. mohor 8160d 15h /dbg_interface/tags/rel_22

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