OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_8] - Rev 36

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
36 Structure changed. Hooks for jtag chain added. mohor 8186d 17h /dbg_interface/tags/rel_8
35 Dbg support datasheet added to cvs. mohor 8210d 22h /dbg_interface/tags/rel_8
34 Product brief added to cvs. mohor 8211d 16h /dbg_interface/tags/rel_8
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8216d 20h /dbg_interface/tags/rel_8
32 Stupid bug that was entered by previous update fixed. mohor 8217d 19h /dbg_interface/tags/rel_8
31 trst synchronization is not needed and was removed. mohor 8217d 20h /dbg_interface/tags/rel_8
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.
mohor 8229d 01h /dbg_interface/tags/rel_8
29 Document revised and put tp better form. mohor 8232d 14h /dbg_interface/tags/rel_8
28 TDO and TDO Enable signal are separated into two signals. mohor 8264d 21h /dbg_interface/tags/rel_8
27 Warnings from synthesys tools fixed. mohor 8278d 22h /dbg_interface/tags/rel_8
26 Warnings from synthesys tools fixed. mohor 8278d 23h /dbg_interface/tags/rel_8
25 trst signal is synchronized to wb_clk_i. mohor 8279d 19h /dbg_interface/tags/rel_8
24 CRC changed so more thorough testing is done. mohor 8280d 21h /dbg_interface/tags/rel_8
23 Trace disabled by default. mohor 8286d 23h /dbg_interface/tags/rel_8
22 Register length fixed. mohor 8286d 23h /dbg_interface/tags/rel_8
21 CRC is returned when chain selection data is transmitted. mohor 8287d 19h /dbg_interface/tags/rel_8
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8288d 22h /dbg_interface/tags/rel_8
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8300d 22h /dbg_interface/tags/rel_8
18 Reset signals are not combined any more. mohor 8303d 07h /dbg_interface/tags/rel_8
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8326d 21h /dbg_interface/tags/rel_8
16 bs_chain_o port added. mohor 8328d 21h /dbg_interface/tags/rel_8
15 bs_chain_o added. mohor 8328d 22h /dbg_interface/tags/rel_8
14 Document updated. mohor 8329d 20h /dbg_interface/tags/rel_8
13 Signal names changed to lowercase. mohor 8329d 22h /dbg_interface/tags/rel_8
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.
mohor 8330d 23h /dbg_interface/tags/rel_8
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8351d 19h /dbg_interface/tags/rel_8
10 First official release 1.0. mohor 8355d 22h /dbg_interface/tags/rel_8
9 Working version. Few bugs fixed, comments added. mohor 8355d 22h /dbg_interface/tags/rel_8
8 Asynchronous set/reset not used in trace any more. mohor 8356d 21h /dbg_interface/tags/rel_8
7 First official release 1.0. mohor 8356d 21h /dbg_interface/tags/rel_8

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.