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[/] [dbg_interface/] [tags/] [rev_23] - Rev 158

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158 root 5606d 10h /dbg_interface/tags/rev_23
149 This commit was manufactured by cvs2svn to create tag 'rev_23'. 7406d 16h /tags/rev_23
147 CPU_WR_CTRL and CPU_RD_CTRL defines changed. igorm 7406d 16h /trunk
146 Changes for the FormalPRO. igorm 7410d 12h /trunk
145 Support for 2 CPUs added. igorm 7410d 17h /trunk
144 Port names and defines for the supported CPUs changed. igorm 7410d 18h /trunk
143 Signals for easier debugging removed. igorm 7410d 19h /trunk
142 Typo fixed. igorm 7410d 20h /trunk
141 data_cnt_lim length changed to reduce number of warnings. igorm 7411d 15h /trunk
140 CRC checking of incoming CRC added to all tasks. igorm 7412d 06h /trunk
139 New release of the debug interface (3rd. release). igorm 7414d 09h /trunk
138 Temp version before changing dbg interface. igorm 7420d 13h /trunk
136 Table describing chain codes added. igorm 7424d 14h /trunk
135 'hz changed to 1'hz because Icarus complains. igorm 7427d 13h /trunk
132 Documentation updated. Many missing things added. igorm 7428d 12h /trunk
131 Documentation updated. Many missing things added. igorm 7428d 13h /trunk
129 New documentation. mohor 7470d 11h /trunk
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7472d 19h /trunk
126 run_sim.scr renamed to run_sim for VATS. mohor 7475d 19h /trunk
124 Display for VATS added. mohor 7477d 15h /trunk
123 All flipflops are reset. mohor 7477d 16h /trunk
121 Port signals are all set to zero after reset. mohor 7480d 16h /trunk
120 test stall_test added. mohor 7480d 19h /trunk
119 cpu_stall_o activated as soon as bp occurs. mohor 7480d 19h /trunk
117 Define name changed. mohor 7482d 15h /trunk
116 Data latching changed when testing WB. mohor 7482d 16h /trunk
115 More debug data added. mohor 7482d 19h /trunk
114 CRC generation iand verification in bench changed. mohor 7482d 21h /trunk
113 IDCODE test improved. mohor 7482d 22h /trunk
112 dbg_tb_defines.v not used. mohor 7483d 16h /trunk

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