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[/] [dbg_interface/] [tags/] [rev_23] - Rev 75

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Rev Log message Author Age Path
75 Simulation files. mohor 7601d 23h /dbg_interface/tags/rev_23
74 Removed. mohor 7601d 23h /dbg_interface/tags/rev_23
73 CRC logic changed. mohor 7601d 23h /dbg_interface/tags/rev_23
71 Mbist support added. simons 7604d 05h /dbg_interface/tags/rev_23
70 A pdf copy of existing doc document. simons 7611d 07h /dbg_interface/tags/rev_23
69 WBCNTL added, multiple CPU support described. simons 7631d 21h /dbg_interface/tags/rev_23
67 Lower two address lines must be always zero. simons 7637d 01h /dbg_interface/tags/rev_23
65 WB_CNTL register added, some syncronization fixes. simons 7638d 00h /dbg_interface/tags/rev_23
63 Three more chains added for cpu debug access. simons 7658d 01h /dbg_interface/tags/rev_23
61 Lapsus fixed. simons 7686d 01h /dbg_interface/tags/rev_23
59 Reset value for riscsel register set to 1. simons 7686d 01h /dbg_interface/tags/rev_23
57 Multiple cpu support added. simons 7686d 03h /dbg_interface/tags/rev_23
56 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7952d 23h /dbg_interface/tags/rev_23
55 Revision 1.6. Trst changed to active high !!!. In order to be compliant with the
standard, reset needs to be negated on the upper layer.		 mohor 7952d 23h /dbg_interface/tags/rev_23
53 Trst active high. Inverted on higher layer. mohor 7953d 01h /dbg_interface/tags/rev_23
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7953d 01h /dbg_interface/tags/rev_23
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7980d 12h /dbg_interface/tags/rev_23
50 Revision 1.5 of the document ready. WISHBONE Scan Chain changed. mohor 7980d 13h /dbg_interface/tags/rev_23
47 mon_cntl_o signals that controls monitor mux added. mohor 8136d 00h /dbg_interface/tags/rev_23
46 Asynchronous reset used instead of synchronous. mohor 8144d 06h /dbg_interface/tags/rev_23
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8151d 02h /dbg_interface/tags/rev_23
44 Signal names changed to lower case. mohor 8151d 02h /dbg_interface/tags/rev_23
43 Intentional error removed. mohor 8156d 02h /dbg_interface/tags/rev_23
42 A block for checking possible simulation/synthesis missmatch added. mohor 8156d 04h /dbg_interface/tags/rev_23
41 Function changed to logic because of some synthesis warnings. mohor 8164d 01h /dbg_interface/tags/rev_23
40 Signal tdo_padoe_o changed back to tdo_padoen_o. mohor 8178d 01h /dbg_interface/tags/rev_23
39 tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just
not named correctly.		 mohor 8179d 02h /dbg_interface/tags/rev_23
38 Few outputs for boundary scan chain added. mohor 8192d 01h /dbg_interface/tags/rev_23
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8192d 05h /dbg_interface/tags/rev_23
36 Structure changed. Hooks for jtag chain added. mohor 8196d 00h /dbg_interface/tags/rev_23

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