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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] - Rev 158

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Rev	Log message	Author	Age	Path
158		root	5588d 12h	/dbg_interface/tags/sdram_test_working/rtl
49	This commit was manufactured by cvs2svn to create tag 'sdram_test_working'.		8087d 17h	/dbg_interface/tags/sdram_test_working/rtl
47	mon_cntl_o signals that controls monitor mux added.	mohor	8087d 17h	/dbg_interface/tags/sdram_test_working/rtl
46	Asynchronous reset used instead of synchronous.	mohor	8095d 23h	/dbg_interface/tags/sdram_test_working/rtl
45	tdo_padoen_o changed to tdo_padoe_o. Signal is active high.	mohor	8102d 19h	/dbg_interface/tags/sdram_test_working/rtl
44	Signal names changed to lower case.	mohor	8102d 19h	/dbg_interface/tags/sdram_test_working/rtl
43	Intentional error removed.	mohor	8107d 19h	/dbg_interface/tags/sdram_test_working/rtl
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8107d 21h	/dbg_interface/tags/sdram_test_working/rtl
41	Function changed to logic because of some synthesis warnings.	mohor	8115d 18h	/dbg_interface/tags/sdram_test_working/rtl
40	Signal tdo_padoe_o changed back to tdo_padoen_o.	mohor	8129d 18h	/dbg_interface/tags/sdram_test_working/rtl
39	tdo_padoen_o changed to tdo_padoe_o. Signal was always active high, just not named correctly.	mohor	8130d 19h	/dbg_interface/tags/sdram_test_working/rtl
38	Few outputs for boundary scan chain added.	mohor	8143d 18h	/dbg_interface/tags/sdram_test_working/rtl
37	tap_top and dbg_top modules are put into two separate modules. tap_top contains only tap state machine and related logic. dbg_top contains all logic necessery for debugging.	mohor	8143d 22h	/dbg_interface/tags/sdram_test_working/rtl
36	Structure changed. Hooks for jtag chain added.	mohor	8147d 17h	/dbg_interface/tags/sdram_test_working/rtl
33	LatchedJTAG_IR used when muxing TDO instead of JTAG_IR.	mohor	8177d 20h	/dbg_interface/tags/sdram_test_working/rtl
32	Stupid bug that was entered by previous update fixed.	mohor	8178d 19h	/dbg_interface/tags/sdram_test_working/rtl
31	trst synchronization is not needed and was removed.	mohor	8178d 19h	/dbg_interface/tags/sdram_test_working/rtl
30	IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in not filled-in. Tested in hw.	mohor	8190d 00h	/dbg_interface/tags/sdram_test_working/rtl
28	TDO and TDO Enable signal are separated into two signals.	mohor	8225d 21h	/dbg_interface/tags/sdram_test_working/rtl
27	Warnings from synthesys tools fixed.	mohor	8239d 22h	/dbg_interface/tags/sdram_test_working/rtl
26	Warnings from synthesys tools fixed.	mohor	8239d 22h	/dbg_interface/tags/sdram_test_working/rtl
25	trst signal is synchronized to wb_clk_i.	mohor	8240d 19h	/dbg_interface/tags/sdram_test_working/rtl
23	Trace disabled by default.	mohor	8247d 22h	/dbg_interface/tags/sdram_test_working/rtl
22	Register length fixed.	mohor	8247d 23h	/dbg_interface/tags/sdram_test_working/rtl
21	CRC is returned when chain selection data is transmitted.	mohor	8248d 18h	/dbg_interface/tags/sdram_test_working/rtl
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8249d 21h	/dbg_interface/tags/sdram_test_working/rtl
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8261d 22h	/dbg_interface/tags/sdram_test_working/rtl
18	Reset signals are not combined any more.	mohor	8264d 07h	/dbg_interface/tags/sdram_test_working/rtl
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8287d 20h	/dbg_interface/tags/sdram_test_working/rtl
15	bs_chain_o added.	mohor	8289d 21h	/dbg_interface/tags/sdram_test_working/rtl

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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] - Rev 158

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