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[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] [dbg_top.v] - Rev 158

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158 root 5584d 14h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
49 This commit was manufactured by cvs2svn to create tag 'sdram_test_working'. 8083d 19h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8083d 19h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
44 Signal names changed to lower case. mohor 8098d 21h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
43 Intentional error removed. mohor 8103d 20h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
42 A block for checking possible simulation/synthesis missmatch added. mohor 8103d 22h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8139d 23h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
36 Structure changed. Hooks for jtag chain added. mohor 8143d 18h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8173d 21h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
32 Stupid bug that was entered by previous update fixed. mohor 8174d 20h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
31 trst synchronization is not needed and was removed. mohor 8174d 21h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8186d 02h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
28 TDO and TDO Enable signal are separated into two signals. mohor 8221d 22h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
25 trst signal is synchronized to wb_clk_i. mohor 8236d 20h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
22 Register length fixed. mohor 8244d 00h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
21 CRC is returned when chain selection data is transmitted. mohor 8244d 20h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8245d 23h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8257d 23h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
18 Reset signals are not combined any more. mohor 8260d 08h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.		 mohor 8283d 22h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
15 bs_chain_o added. mohor 8285d 23h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
13 Signal names changed to lowercase. mohor 8286d 23h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.		 mohor 8288d 00h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8308d 19h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
9 Working version. Few bugs fixed, comments added. mohor 8312d 23h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
8 Asynchronous set/reset not used in trace any more. mohor 8313d 22h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
5 Trace fixed. Some registers changed, trace simplified. mohor 8314d 19h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v
2 Initial official release. mohor 8319d 20h /dbg_interface/tags/sdram_test_working/rtl/verilog/dbg_top.v

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