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[/] [dbg_interface/] [trunk/] [bench/] [verilog/] - Rev 158

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Rev Log message Author Age Path
158 root 5599d 07h /dbg_interface/trunk/bench/verilog
145 Support for 2 CPUs added. igorm 7403d 14h /dbg_interface/trunk/bench/verilog
142 Typo fixed. igorm 7403d 17h /dbg_interface/trunk/bench/verilog
141 data_cnt_lim length changed to reduce number of warnings. igorm 7404d 12h /dbg_interface/trunk/bench/verilog
140 CRC checking of incoming CRC added to all tasks. igorm 7405d 04h /dbg_interface/trunk/bench/verilog
139 New release of the debug interface (3rd. release). igorm 7407d 06h /dbg_interface/trunk/bench/verilog
138 Temp version before changing dbg interface. igorm 7413d 10h /dbg_interface/trunk/bench/verilog
135 'hz changed to 1'hz because Icarus complains. igorm 7420d 11h /dbg_interface/trunk/bench/verilog
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7465d 17h /dbg_interface/trunk/bench/verilog
124 Display for VATS added. mohor 7470d 13h /dbg_interface/trunk/bench/verilog
121 Port signals are all set to zero after reset. mohor 7473d 13h /dbg_interface/trunk/bench/verilog
120 test stall_test added. mohor 7473d 16h /dbg_interface/trunk/bench/verilog
117 Define name changed. mohor 7475d 13h /dbg_interface/trunk/bench/verilog
116 Data latching changed when testing WB. mohor 7475d 13h /dbg_interface/trunk/bench/verilog
115 More debug data added. mohor 7475d 17h /dbg_interface/trunk/bench/verilog
114 CRC generation iand verification in bench changed. mohor 7475d 18h /dbg_interface/trunk/bench/verilog
113 IDCODE test improved. mohor 7475d 19h /dbg_interface/trunk/bench/verilog
112 dbg_tb_defines.v not used. mohor 7476d 14h /dbg_interface/trunk/bench/verilog
111 Define tap_defines.v added to test bench. mohor 7476d 14h /dbg_interface/trunk/bench/verilog
110 Waiting for "ready" improved. mohor 7476d 14h /dbg_interface/trunk/bench/verilog
102 New version. mohor 7478d 09h /dbg_interface/trunk/bench/verilog
101 Almost finished. mohor 7478d 10h /dbg_interface/trunk/bench/verilog
99 cpu registers added. mohor 7479d 12h /dbg_interface/trunk/bench/verilog
96 Working. mohor 7480d 16h /dbg_interface/trunk/bench/verilog
95 Temp version. mohor 7481d 04h /dbg_interface/trunk/bench/verilog
93 tmp version. mohor 7482d 15h /dbg_interface/trunk/bench/verilog
92 temp version. mohor 7485d 19h /dbg_interface/trunk/bench/verilog
91 tmp version. mohor 7486d 14h /dbg_interface/trunk/bench/verilog
90 tmp version. mohor 7487d 09h /dbg_interface/trunk/bench/verilog
89 temp4 version. mohor 7488d 15h /dbg_interface/trunk/bench/verilog

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