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[/] [dbg_interface/] [trunk/] [bench/] [verilog] - Rev 140

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Rev Log message Author Age Path
140 CRC checking of incoming CRC added to all tasks. igorm 7429d 11h /dbg_interface/trunk/bench/verilog
139 New release of the debug interface (3rd. release). igorm 7431d 14h /dbg_interface/trunk/bench/verilog
138 Temp version before changing dbg interface. igorm 7437d 18h /dbg_interface/trunk/bench/verilog
135 'hz changed to 1'hz because Icarus complains. igorm 7444d 18h /dbg_interface/trunk/bench/verilog
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7490d 00h /dbg_interface/trunk/bench/verilog
124 Display for VATS added. mohor 7494d 20h /dbg_interface/trunk/bench/verilog
121 Port signals are all set to zero after reset. mohor 7497d 20h /dbg_interface/trunk/bench/verilog
120 test stall_test added. mohor 7497d 23h /dbg_interface/trunk/bench/verilog
117 Define name changed. mohor 7499d 20h /dbg_interface/trunk/bench/verilog
116 Data latching changed when testing WB. mohor 7499d 20h /dbg_interface/trunk/bench/verilog
115 More debug data added. mohor 7500d 00h /dbg_interface/trunk/bench/verilog
114 CRC generation iand verification in bench changed. mohor 7500d 01h /dbg_interface/trunk/bench/verilog
113 IDCODE test improved. mohor 7500d 02h /dbg_interface/trunk/bench/verilog
112 dbg_tb_defines.v not used. mohor 7500d 21h /dbg_interface/trunk/bench/verilog
111 Define tap_defines.v added to test bench. mohor 7500d 21h /dbg_interface/trunk/bench/verilog
110 Waiting for "ready" improved. mohor 7500d 22h /dbg_interface/trunk/bench/verilog
102 New version. mohor 7502d 16h /dbg_interface/trunk/bench/verilog
101 Almost finished. mohor 7502d 17h /dbg_interface/trunk/bench/verilog
99 cpu registers added. mohor 7503d 20h /dbg_interface/trunk/bench/verilog
96 Working. mohor 7505d 00h /dbg_interface/trunk/bench/verilog
95 Temp version. mohor 7505d 11h /dbg_interface/trunk/bench/verilog
93 tmp version. mohor 7506d 23h /dbg_interface/trunk/bench/verilog
92 temp version. mohor 7510d 03h /dbg_interface/trunk/bench/verilog
91 tmp version. mohor 7510d 22h /dbg_interface/trunk/bench/verilog
90 tmp version. mohor 7511d 17h /dbg_interface/trunk/bench/verilog
89 temp4 version. mohor 7512d 22h /dbg_interface/trunk/bench/verilog
88 temp3 version. mohor 7513d 17h /dbg_interface/trunk/bench/verilog
87 tmp2 version. mohor 7514d 22h /dbg_interface/trunk/bench/verilog
80 New version of the debug interface. Not finished, yet. mohor 7527d 20h /dbg_interface/trunk/bench/verilog
75 Simulation files. mohor 7588d 18h /dbg_interface/trunk/bench/verilog

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