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[/] [dbg_interface/] [trunk/] [rtl/] [verilog/] [dbg_top.v] - Rev 144

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Rev Log message Author Age Path
144 Port names and defines for the supported CPUs changed. igorm 7434d 08h /dbg_interface/trunk/rtl/verilog/dbg_top.v
139 New release of the debug interface (3rd. release). igorm 7437d 23h /dbg_interface/trunk/rtl/verilog/dbg_top.v
138 Temp version before changing dbg interface. igorm 7444d 03h /dbg_interface/trunk/rtl/verilog/dbg_top.v
128 Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
turned on.		 mohor 7496d 09h /dbg_interface/trunk/rtl/verilog/dbg_top.v
123 All flipflops are reset. mohor 7501d 06h /dbg_interface/trunk/rtl/verilog/dbg_top.v
117 Define name changed. mohor 7506d 05h /dbg_interface/trunk/rtl/verilog/dbg_top.v
108 Reset values width added because of FV, a good sentence changed because some tools can not handle it. simons 7507d 12h /dbg_interface/trunk/rtl/verilog/dbg_top.v
106 Sensitivity list updated. simons 7508d 10h /dbg_interface/trunk/rtl/verilog/dbg_top.v
101 Almost finished. mohor 7509d 03h /dbg_interface/trunk/rtl/verilog/dbg_top.v
99 cpu registers added. mohor 7510d 05h /dbg_interface/trunk/rtl/verilog/dbg_top.v
95 Temp version. mohor 7511d 21h /dbg_interface/trunk/rtl/verilog/dbg_top.v
81 New directory structure. New version of the debug interface.
Files that are not needed removed.		 mohor 7534d 05h /dbg_interface/trunk/rtl/verilog/dbg_top.v
73 CRC logic changed. mohor 7595d 03h /dbg_interface/trunk/rtl/verilog/dbg_top.v
67 Lower two address lines must be always zero. simons 7630d 06h /dbg_interface/trunk/rtl/verilog/dbg_top.v
65 WB_CNTL register added, some syncronization fixes. simons 7631d 05h /dbg_interface/trunk/rtl/verilog/dbg_top.v
63 Three more chains added for cpu debug access. simons 7651d 06h /dbg_interface/trunk/rtl/verilog/dbg_top.v
57 Multiple cpu support added. simons 7679d 07h /dbg_interface/trunk/rtl/verilog/dbg_top.v
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7946d 05h /dbg_interface/trunk/rtl/verilog/dbg_top.v
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7973d 17h /dbg_interface/trunk/rtl/verilog/dbg_top.v
47 mon_cntl_o signals that controls monitor mux added. mohor 8129d 05h /dbg_interface/trunk/rtl/verilog/dbg_top.v
44 Signal names changed to lower case. mohor 8144d 07h /dbg_interface/trunk/rtl/verilog/dbg_top.v
43 Intentional error removed. mohor 8149d 06h /dbg_interface/trunk/rtl/verilog/dbg_top.v
42 A block for checking possible simulation/synthesis missmatch added. mohor 8149d 08h /dbg_interface/trunk/rtl/verilog/dbg_top.v
37 tap_top and dbg_top modules are put into two separate modules. tap_top
contains only tap state machine and related logic. dbg_top contains all
logic necessery for debugging.		 mohor 8185d 09h /dbg_interface/trunk/rtl/verilog/dbg_top.v
36 Structure changed. Hooks for jtag chain added. mohor 8189d 04h /dbg_interface/trunk/rtl/verilog/dbg_top.v
33 LatchedJTAG_IR used when muxing TDO instead of JTAG_IR. mohor 8219d 07h /dbg_interface/trunk/rtl/verilog/dbg_top.v
32 Stupid bug that was entered by previous update fixed. mohor 8220d 06h /dbg_interface/trunk/rtl/verilog/dbg_top.v
31 trst synchronization is not needed and was removed. mohor 8220d 07h /dbg_interface/trunk/rtl/verilog/dbg_top.v
30 IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
not filled-in. Tested in hw.		 mohor 8231d 12h /dbg_interface/trunk/rtl/verilog/dbg_top.v
28 TDO and TDO Enable signal are separated into two signals. mohor 8267d 08h /dbg_interface/trunk/rtl/verilog/dbg_top.v

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