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[/] [ethmac/] [branches/] [unneback/] - Rev 362

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Rev Log message Author Age Path
362 added Makefiles to build project unneback 4690d 12h /ethmac/branches/unneback
361 created branch unneback unneback 4690d 12h /ethmac/branches/unneback
352 Removed delayed assignments from rtl code olof 4701d 13h /ethmac/trunk
351 Turn defines into parameters in eth_cop olof 4710d 03h /ethmac/trunk
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4710d 04h /ethmac/trunk
349 Make all parameters configurable from top level olof 4711d 04h /ethmac/trunk
348 Added option to dump VCD files olof 4712d 03h /ethmac/trunk
347 Added information about running with Icarus Verilog olof 4712d 04h /ethmac/trunk
346 Updated project location olof 4712d 06h /ethmac/trunk
345 Temporarily disable failing tests olof 4712d 08h /ethmac/trunk
344 bit 9 in phy control register is self clearing olof 4718d 10h /ethmac/trunk
343 Address miss should not be asserted on short frames olof 4722d 06h /ethmac/trunk
342 Added cast to avoid inequality when comparing different data types olof 4722d 06h /ethmac/trunk
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4722d 06h /ethmac/trunk
340 Don't fail if log dir already exists olof 4723d 03h /ethmac/trunk
339 Added basic support for Icarus Verilog olof 4724d 03h /ethmac/trunk
338 root 5516d 09h /ethmac/trunk
335 New directory structure. root 5573d 14h /ethernet/trunk
334 Minor fixes for Icarus simulator. igorm 7021d 16h /trunk
333 Some small fixes + some troubles fixed. igorm 7022d 04h /trunk
332 Case statement improved for synthesys. igorm 7035d 09h /trunk
331 Tests for delayed CRC and defer indication added. igorm 7050d 11h /trunk
330 Warning fixes. igorm 7050d 11h /trunk
329 Defer indication fixed. igorm 7050d 12h /trunk
328 Delayed CRC fixed. igorm 7050d 12h /trunk
327 Defer indication fixed. igorm 7050d 13h /trunk
326 Delayed CRC fixed. igorm 7050d 13h /trunk
325 Defer indication fixed. igorm 7050d 13h /trunk
323 Accidently deleted line put back. igorm 7347d 13h /trunk
321 - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
previous update of the core.
- TxBDAddress is set to 0 after the TX is enabled in the MODER register.
- RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
register. (thanks to Mathias and Torbjorn)
- Multicast reception was fixed. Thanks to Ulrich Gries		 igorm 7351d 08h /trunk

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