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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 350

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Rev	Log message	Author	Age	Path
350	Turn M[1-2]_ADDRESSED_S[1-2] defines into wires	olof	4710d 04h	/ethmac/branches/unneback/rtl/verilog
349	Make all parameters configurable from top level	olof	4711d 05h	/ethmac/branches/unneback/rtl/verilog
346	Updated project location	olof	4712d 06h	/ethmac/branches/unneback/rtl/verilog
341	Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short	olof	4722d 06h	/ethmac/branches/unneback/rtl/verilog
338		root	5516d 09h	/ethmac/branches/unneback/rtl/verilog
335	New directory structure.	root	5573d 14h	/ethmac/branches/unneback/rtl/verilog
333	Some small fixes + some troubles fixed.	igorm	7022d 04h	/ethmac/branches/unneback/rtl/verilog
332	Case statement improved for synthesys.	igorm	7035d 09h	/ethmac/branches/unneback/rtl/verilog
330	Warning fixes.	igorm	7050d 11h	/ethmac/branches/unneback/rtl/verilog
329	Defer indication fixed.	igorm	7050d 12h	/ethmac/branches/unneback/rtl/verilog
328	Delayed CRC fixed.	igorm	7050d 12h	/ethmac/branches/unneback/rtl/verilog
327	Defer indication fixed.	igorm	7050d 13h	/ethmac/branches/unneback/rtl/verilog
326	Delayed CRC fixed.	igorm	7050d 13h	/ethmac/branches/unneback/rtl/verilog
325	Defer indication fixed.	igorm	7050d 13h	/ethmac/branches/unneback/rtl/verilog
323	Accidently deleted line put back.	igorm	7347d 13h	/ethmac/branches/unneback/rtl/verilog
321	- Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the previous update of the core. - TxBDAddress is set to 0 after the TX is enabled in the MODER register. - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER register. (thanks to Mathias and Torbjorn) - Multicast reception was fixed. Thanks to Ulrich Gries	igorm	7351d 08h	/ethmac/branches/unneback/rtl/verilog
320	TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.	igorm	7351d 12h	/ethmac/branches/unneback/rtl/verilog
317	Multicast detection fixed. Only the LSB of the first byte is checked.	igorm	7391d 14h	/ethmac/branches/unneback/rtl/verilog
312	Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.	tadejm	7494d 11h	/ethmac/branches/unneback/rtl/verilog
306	Lapsus fixed (!we -> ~we).	simons	7495d 09h	/ethmac/branches/unneback/rtl/verilog
304	WISHBONE slave changed and tested from only 32-bit accesss to byte access.	tadejm	7517d 05h	/ethmac/branches/unneback/rtl/verilog
302	mbist signals updated according to newest convention	markom	7543d 16h	/ethmac/branches/unneback/rtl/verilog
301	Update RxEnSync only when mrxdv_pad_i is inactive (LOW).	knguyen	7554d 08h	/ethmac/branches/unneback/rtl/verilog
297	Artisan ram instance added.	simons	7607d 07h	/ethmac/branches/unneback/rtl/verilog
288	This file was not part of the RTL before, but it should be here.	simons	7643d 09h	/ethmac/branches/unneback/rtl/verilog
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7669d 12h	/ethmac/branches/unneback/rtl/verilog
285	Binary operator used instead of unary (xnor).	mohor	7669d 12h	/ethmac/branches/unneback/rtl/verilog
284	Busy was set 2 cycles too late. Reported by Dennis Scott.	mohor	7697d 14h	/ethmac/branches/unneback/rtl/verilog
283	RxBDAddress was updated also when value to r_TxBDNum was written with greater value than allowed.	mohor	7725d 07h	/ethmac/branches/unneback/rtl/verilog
280	Reset has priority in some flipflops.	mohor	7803d 09h	/ethmac/branches/unneback/rtl/verilog

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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 350

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